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october 2004 i ? 2004 actel corporation see actel?s website for the latest version of the datasheet rtsx-su radtolerant fpgas (umc) designed for space ? seu-hardened registers eliminate the need to implement triple-module redundancy (tmr) ? immune to single-event upsets (seu) to let th > 40 mev-cm 2 /mg, ? seu rate < 10 ?10 upset/bit-day in worst-case geosynchronous orbit up to 100 krad (si) total ionizing dose (tid) ? parametric performance supported with lot- specific test data single-event latch-up (sel) immunity tm1019.5 test data available qml certified devices high performance 230 mhz system performance 310 mhz internal performance 9.5 ns input clock to output pad specifications 0.25 m metal-to-metal antifuse process (umc) 48,000 to 108,000 available system gates up to 2,012 seu-hardened flip-flops up to 360 user-programmable i/o pins features very low power consumption (up to 68 mw at standby) 3.3v and 5v mixed voltage configurable i/o support for 3.3v/5v pci, lvttl, ttl, and cmos ? 5v input tolerance and 5v drive strength ? slow slew rate option ? configurable weak resi stor pull-up/down for tristated outputs at power-up ? hot-swap compliant with cold-sparing support secure programming technol ogy prevents reverse engineering and design theft 100% circuit resource utilization with 100% pin locking unique in-system diagnostic and verification capability with silicon explorer ii low-cost prototyping option deterministic, user -controllable timing jtag boundary scan testing in compliance with ieee standard 1149.1 ? dedicated jtag reset (trst) pin ? e u table 1 rtsx-su product profile device rtsx32su rtsx72su capacity ty p i c a l g a t e s system gates 32,000 48,000 72,000 108,000 logic modules combinatorial cells seu-hardened register cells (dedicated flip-flops) 2,880 1,800 1,080 6,036 4,024 2,012 maximum flip-flops 1,980 4,024 maximum user i/os 227 360 clocks 33 quadrant clocks 04 speed grades std., ?1 std., ?1 package (by pin count) cqfp ccga cclg 208, 256 256 208, 256 624 advanced v0.3
rtsx-su radtolerant fpgas (umc) ii advanced v0.3 ordering information temperature grade and application offering ceramic device resources user i/os (including clock buffers) device cqfp 208-pin cqfp 256-pin cclg 256-pin ccga 624-pin rtsx32su 173 227 202 ? rtsx72su 170 212 ? 360 note: the 256-pin cclg available in mil-temp only. package rtsx32su rtsx72su cq208 b, e b, e cq256 b, e b, e cc256 m ? cg624 ? b, e note: m = military temperature b = mil-std-883 class b e = e-flow rtsx72su cq part number package type cq = ceramic quad flat pack cg = ceramic column grid aray 256 b package lead count application (temperature range) b = mil-std-883 class b e = e-flow (actel space level flow) m = military temperature speed grade rtsx32su = standard speed blank = 1 approximately 15% faster than standard = 1 72,000 radtolerant typical gates 32,000 radtolerant typical gates rtsx72su = cc = ceramic chip carrier land grid
rtsx-su radtolerant fpgas (umc) advanced v0.3 iii speed grade and temperature/application matrix qml certification actel has achieved full qml certificati on, demonstrating that quality management procedures, processes, and controls are in place and comply with mil-prf-38535 (the performa nce specification used by the u.s. department of defense for monolithic integrated circuits). actel mil-std-883 class b product flow std. -1 m ?? b ?? e ?? step screen 883 method 883?class b requirement 1. internal visual 2010, test condition b 100% 2. temperature cycling 1010, test condition c 100% 3. constant acceleration 2001, test condition b or d, y 1 , orientation only 100% 4. particle impact noise detection 2020, condition a 100% 5. seal a. fine b. gross 1014 100% 100% 6. visual inspection 2009 100% 7. pre-burn-in electrical parameters in accordance with applicable actel device specification 100% 8. dynamic burn-in 1015, condition d, 160 hours at 125c or 80 hours at 150c 100% 9. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 10. percent defective allowable 5% all lots 11. final electrical test a. static tests (1)25c (subgroup 1, table i) (2)?55c and +125c (subgroups 2, 3, table i) b. functional tests (1)25c (subgroup 7, table i) (2)?55c and +125c (subgroups 8a and 8b, table i) c. switching tests at 25c (subgroup 9, table i) in accordance with applicable actel device specification, wh ich includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 12. external visual 2009 100%
rtsx-su radtolerant fpgas (umc) iv advanced v0.3 actel extended flow 1 step screen method requirement 1. destructive in-line bond pull 3 2011, condition d sample 2. internal visual 2010, condition a 100% 3. serialization 100% 4. temperature cycling 1010, condition c 100% 5. constant acceleration 2001, condition b or d, y 1 orientation only 100% 6. particle impact noise detection 2020, condition a 100% 7. radiographic 2012 (one view only) 100% 8. pre-burn-in test in accordance with ap plicable actel device specification 100% 9. dynamic burn-in 1015, condition d, 240 hours at 125c or 120 hours at 150c minimum 100% 10. interim (post-burn-in) electrical parameters in accordan ce with applicable actel device specification 100% 11. static burn-in 1015, condition c, 72 hours at 150c or 144 hours at 125c minimum 100% 12. interim (post-burn-in) electrical parameters in accordan ce with applicable actel device specification 100% 13. percent defective allowable (pda) calculation 5%, 3% functional parameters at 25c all lots 14. final electrical test a. static tests (1)25c (subgroup 1, table1) (2)?55c and +125c (subgroups 2, 3, table 1) b. functional tests (1)25c (subgroup 7, table 15) (2)?55c and +125c (subgroups 8a and b, table 1) c. switching tests at 25c (subgroup 9, table 1) in accordance with actel applicable device specification which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 100% 15. seal a. fine b. gross 1014 100% 16. external visual 2009 100% notes: 1. actel offers extended flow for users requ iring additional screening beyond mil-std-8 33, class b requirement. actel offers thi s extended flow incorporating the majority of the screening proc edures as outlined in method 500 4 of mil-std-883, class s. the exceptions to method 5004 are shown in notes 2 and 4 below. 2. mil-std-883, method 5004, requires a 100 percent radiation latch-up testing to method 1020. actel will not perform any radiation testing, and this requirement must be waived in its entirety. 3. method 5004 requires a 100 percent, nondestructive bond-pul l to method 2003. actel substitutes a destructive bond-pull to method 2011 condition d on a sample basis only. 4. wafer lot acceptance complies to commercial standards only (requirement per method 5007 is not performed).
advanced v0.3 v table of contents rtsx-su radtolerant fpgas (umc) general description device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 programmable interconnect element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 logic modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 2 routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 global resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 design environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 low-cost prototyping solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 in-system diagnostic and debug capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 radiation survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 detailed specification general conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 6 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 7 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 routing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 global resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 other architectural features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 package pin assignments 208-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 256-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -5 256-pin cclg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 0 624-pin ccga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

rtsx-su radtolerant fpgas (umc) advanced v0.3 1-1 general description rtsx-su radtolerant fpgas are enhanced versions of actel?s sx-a family of devices, specifically designed for enhanced radiation performance. featuring seu-hardened d-type flip-flops that offer the benefits of triple module redundancy (tmr) without the associated overhead, the rt sx-su family is a unique product offering for space applications. manufactured using 0.25 m technology at the united microelectronics corporation (umc) facility in taiwan, rtsx-su offers levels of radiation survivability far in excess of typical cmos devices. device architecture actel's rtsx-su architecture , derived from the highly successful sx-a sea-of-modules architecture, has been designed to improve upset and total-dose performance in radiation environments. with three layers of metal interconnect in the rtsx32su and four metal layers in rtsx72su, the rtsx-su family provides efficient use of silic on by locating the routing interconnect resources between the top two metal layers. this completely elimin ates the channe ls of routing and interconnect resources between logic modules as found in traditional fpga s. in a sea-of-modules architecture, the entire floo r of the fpga is covered with a grid of logic modules with virtually no chip area lost to interconnect elem ents or routing. the rtsx-su architecture adds several enhancements over the sx-a arch itecture to improve its performance in radiation environments, such as seu-hardened flip-flops, wider clock lines, and stronger clock drivers. programmable interconnect elements interconnection between logic modules is achieved using actel?s patented metal-to-metal programmable antifuse interconnect elements. the antifuses are normally open circuit and form a permanent, low-impedance connection when programmed. the metal-to-metal antifuse is made up of a combination of amorphous silicon and dielec tric material with barrier metals and has a programmed (?on? state) resistance of 25 ? with capacitance of 1.0 ff for low signal impedance ( figure 1-1 on page 1-2 ). these antifuse interconnects reside between the top two layers of metal and thereb y enable the sea-of-modules architecture in an fpga. the extremely small size of these interconnect elements gives the rtsx-su family abundant routing resources and provides excellent protection against design theft. reverse engineering is virtually impossi ble because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. additi onally, since rtsx-su is a nonvolatile, single-chip soluti on, there is no configuration bitstream to intercept. the rtsx-su interconnect (i.e., the antifuses and metal tracks) also has lower capacitance and resistance than that of any other device of similar capacity, leading to the fastest signal propagation in the industry for the radiation tolerance offered. i/o structure the rtsx-su family features a flexible i/o structure that supports 3.3v lvttl, 5v ttl , 5v cmos, and 3.3v and 5v pci. all i/o standards are ho t-swap compliant, cold- sparing capable, and 5v tole rant (except for 3.3v pci). in addition, each i/o on an rtsx-su device can be configured as an input, an output, a tristate output, or a bidirectional pin. mixed i/o standards are allowed and can be set on a pin-by-pin basis. high or low slew rate can be set on individual output buffers (except for pci, which defaults to high slew), as well as the power-up configuration (either pull-up or pull-down). even without the inclusion of dedicated i/o registers, these i/os, in combination wi th array registers, can achieve clock-to-output-pad ti ming as fast as 9.5 ns. in most fpgas, i/o cells that have embedded latches and flip-flops require instantiat ion in hdl code; this is a design complication not encountered in rtsx-su fpgas. fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn, enables parallel design of system components and reduces overall design time.
rtsx-su radtolerant fpgas (umc) 1-2 advanced v0.3 logic modules actel?s rtsx-su family provides two types of logic modules to the designer ( figure 1-2 on page 1-3 ): the register cell (r-cell) and th e combinatorial cell (c-cell). the c-cell implements a range of combinatorial functions with up to five inputs. inclusion of the db input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the rtsx-su architecture. an example of the improved flexibility enabled by the inversion capability is the ability to integrate a three-input exclus ive-or function into a single c-cell. this facilitates the c onstruction of nine-bit parity- tree functions. at the same time, the c-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. the r-cell contains a flip-f lop featuring asynchronous clear, asynchronous preset, and clock enable (using the s0 and s1 lines) control si gnals. the r-cell registers feature programmable clock polarity, selectable on a register-by-register basis. this provides additional flexibility during mapping of synthesized functions into the rtsx-su fpga. the clock source for the r-cell can be chosen from the hardwired cl ock, the routed clocks, or the internal logic. while each seu-hardened r-ce ll appears as a single d-type flip-flop to the user, each is implemented employing triple redundancy to achieve a let threshold of greater than 40 mev-cm 2 /mg. each tmr r-cell c onsists of three master- slave latch pairs, each with asynchronous, self-correcting feedback paths. the output of each latch on the master or slave side is voted with the outputs of the other two latches on that side. if one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. care was taken in the layout to ensure that a single ion strike could not affect more than one latch (see the "r-cell" section on page 2-23 for more details). actel has arranged all c-cell and r-cell logic modules into horizontal banks called clus ters. there are two types of clusters: type 1 contains tw o c-cells and one r-cell, while type 2 contains one c-cell and two r-cells. to increase design efficiency and device performance, actel has further organized these modules into superclusters. supercluster 1 is a two-wide grouping of type 1 clusters. supercluster 2 is a two-wide group containing one type 1 cluster and one type 2 cluster. rtsx-su devices feature more supercluster 1 modules than supercluster 2 modules because designers typically require significantly more combinatorial logic than flip- flops ( figure 1-2 on page 1-3 ). figure 1-1 rtsx-su family interconnect elements silicon substrate metal 4 metal 3 metal 2 metal 1 amorphous silicon/ dielectric antifuse tungsten plug via tungsten plug via tungsten plug contact routing tracks
rtsx-su radtolerant fpgas (umc) advanced v0.3 1-3 routing r-cells and c-cells within cl usters and superclusters can be connected through the use of two innovative local routing resources called fastconnect and directconnect , which enable extremely fast and predictable interconnection of modules within clusters and superclusters. this routing ar chitecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance ( figure 1-3 and figure 1-4 on page 1-4 ). directconnect is a horizontal routing resource that provides connections from a c-cell to its neighboring r-cell in a given supercluster. directconnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagatio n time of less than 0.1 ns. fastconnect enables horizontal routing between any two logic modules within a given supercluster and vertical routing with the supercluster immediately below it. only one programmab le connection is used in a fastconnect path, delivering a maximum interconnect propagation delay of 0.4 ns. in addition to directconnect and fastconnect, the architecture makes use of tw o globally-oriented routing resources known as segmented routing and high-drive routing. actel?s segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic plac e-and-route software to minimize signal propagation delays. figure 1-2 r-cell, c-cell and cluster organization type 1 supercluster type 2 supercluster cluster 1 cluster 1 cluster 2 cluster 1 r-cell c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y direct connect input clka, clkb, internal logic hclk cks ckp clr pre y dq routed data input s0 s1
rtsx-su radtolerant fpgas (umc) 1-4 advanced v0.3 figure 1-3 directconnect and fastconnect for supercluster 1?s figure 1-4 directconnect and fastconnect for supercluster 2?s type 1 superclusters routing segments typically 2 antifuses max. 5 antifuses fastconnect one antifuse directconnect no antifuses for smallest routing delay type 2 superclusters routing segments typically 2 antifuses max. 5 antifuses fastconnect one antifuse directconnect no antifuses for smallest routing delay
rtsx-su radtolerant fpgas (umc) advanced v0.3 1-5 global resources actel?s high-drive routing structure provides three clock networks: hardwired clocks (hclk), routed clocks (clka, clkb), and quadrant clocks (qclka, qclkb, qclkc, qclkd) ( table 1-1 ). the first clock, called hclk, is hardwired from the hclk buffer to the clock select mux in each r-cell. hclk cannot be connected to combinational logic. this provides a fast propagation path for the clock signal, enabling the 9.5 ns clock-to-out (pad-to-pad) performance of the rtsx-su devices. the second type of clock, routed clocks (clka, clkb), are global clocks that can be sourced from either external pins or internal logic signals within the device. clka and clkb may be connected to sequential cells (r-cells) or to combinational logic (c-cells). the last type of clock, quadrant clocks, are only found in the rtsx72su. similar to th e routed clocks, the four quadrant clocks (qclka, qclkb, qclkc, qclkd) can be sourced from external pins or from internal logic signals within the device. each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. design environment the rtsx-su radtolerant family of fpgas is fully supported by both actel's libero? integrated design environment (ide) and desi gner fpga development software. actel libero ide is a design management environment, seamlessly in tegrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment. libero ide includes synplify? for actel from synplicity?, viewdraw for actel from mentor graphics, model sim ? hdl simulator from mentor graphics?, waveformer lite? from synapticad?, and designer software from actel. refer to the libero ide flow (located on actel?s website) diagram for more information. actel's designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for fpga development. the designer software includes timing-driven place-and-ro ute, and a world-class integrated static timing anal yzer and constraints editor. with the designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, actel?s integrated verification and logic analysis tool. another tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as mentor gr aphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. programming programming support is provided through actel's silicon sculptor ii, a single-site pr ogrammer driven via a pc- based gui. factory programming is available as well. low-cost prototyping solution since the enhanced radiation characteristics of radiation- tolerant devices are not required during the prototyping phase of the design, actel has developed a prototyping solution for rtsx-su that utilizes commercial sx-a devices. the prototyping solution consists of two parts: a well-documented design flow that allows the customer to target an rtsx-su design to the equivalent commercial sx-a device either footprint-compatible packages or prototyping sockets to adapt commercial sx-a packages to the rtsx-su package footprints this methodology provides th e user with a cost-effective solution while maintaining the short time-to-market associated with actel fpgas . please see the application note prototyping for the rtsx-s enhanced aerospace fpga for more details table 1-1 rtsx-su global resources rtsx32su rtsx72su routed clocks (clka, clkb) 2 2 hardwired clocks (hclk) 1 1 quadrant clocks (qclka, qclkb, qclkc, qclkd) 04
rtsx-su radtolerant fpgas (umc) 1-6 advanced v0.3 in-system diagnostic and debug capabilities the rtsx-su family of fpgas includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the fpga without disturbing normal device operation. two individual signals can be brought out to two multipurpose pins (pra and prb) on the device. the probe circuitry is accessed and controlled vi a silicon explorer ii, actel's integrated verification and logic analysis tool, which attaches to the serial port of a pc and communicates with the fpga via the jtag port. see figure 1-5 . radiation survivability the rtsx-su radtolerant devices have varying total-dose radiation survivability. the ability of these devices to survive radiation effects is both device and lot dependent. total-dose results are summar ized in two ways. the first summary is indicated by the maximum total-dose level achieved before the device fails to meet an individual performance specification but remains functional. for actel fpgas, the parameter that first exceeds the specification is i cc (standby supply current). the second summary is indicated by the maximum total dose achieved prior to the functional failure of the device. actel provides total-dose radiation test data on each lot. reports are available on actel?s website or from actel?s local sales representatives. listings of available lots and devices can also be provided. for a radiation performance summary, see radiation data . this summary also shows single-event upset (seu) and single-event latch-up (sel) testing that has been performed on actel fpgas. all radiation performance in formation is provided for informational purposes only and is not guaranteed. total dose effects are lot-dependent, and actel does not guarantee that future device s will continue to exhibit similar radiation characteri stics. in addition, actual performance can vary widely due to a variety of factors, including but not limited to, characteristics of the orbit, radiation environment, pr oximity to the satellite exterior, the amount of inherent shielding from other sources within the satellit e, and actual bare die variations. for these reasons, it is the sole responsibility of the user to determine whether the device will meet the requirements of the specific design. summary the rtsx-su family of radtolerant fpgas extends actel?s highly successful offering of fpgas for radiation environments with the industry?s first fpga designed specifically for enhanced radiation performance. figure 1-5 probe setup silicon explorer ii tdi tck tdo tms pra prb serial connection 16 additional channels rtsx-su fpga
rtsx-su radtolerant fpgas (umc) advanced v0.3 1-7 related documents application notes simultaneous switching no ise and signal integrity http://www.actel.com /documents/sso.pdf implementation of security in actel antifuse fpgas http://www.actel.com/documen ts/antifusesecurityan.pdf using a54sx72a and rt54s x72s quadrant clocks http://www.actel.com /documents/qclk.pdf actel ex, sx-a and rtsx-s i/os http://www.actel.com/docum ents/antifuseioan.pdf ieee standard 1149.1 (jtag) in th e sx/rtsx/sx-a/ex/rt54sx-s families http://www.actel.com/doc uments/sx_sxajtag.pdf prototyping for the rt54sx- s enhanced aerospace fpga http://www.actel.com/doc uments/rt54s xproto.pdf actel cqfp to fbfa adapter socket instructions http://www.actel.com/documen ts/cq352-fpga_adapter_an.pdf actel sx-a and rt54sx-s devices in ho t-swap and cold-spa ring applications http://www.actel.com/documen ts/hotswapcoldsparing.pdf user?s guides and manuals antifuse macro library guide http://www.actel.com/documents/libguide.pdf actgen macros user?s guide http://www.actel.com/documents/genguide.pdf libero ide v5.2 user's guide http://www.actel.com/d ocuments/liberoug.pdf silicon sculptor ii user?s guide http://www.actel.com/techd ocs/manuals/default.asp white papers design security in nonvolat ile flash and antifuse fpgas http://www.actel.com/docum ents/designsecurity.pdf understanding actel antifuse device security http://www.actel.com/documen ts/antifusesecuritywp.pdf

rtsx-su radtolerant fpgas (umc) advanced v0.3 2-1 detailed specifications general conditions power-up and power-cycling the rtsx-su family does not require any sp ecific power-up or power-cycling sequence. table 2-1 supply voltages v cca v cci maximum input tolerance maximum output drive 2.5v 3.3v 5v* 3.3v 2.5v 5v 5v 5v note: *3.3v pci is not 5v tolerant table 2-2 characteristics for al l i/o configurations i/o standard hot swappable slew rate control power-up resistor pull ttl, lvttl yes yes. affects falling edge outputs only pull-up or pull-down 3.3v pci no no. high slew rate only pull-up or pull-down 5v pci yes no. high slew rate only pull-up or pull-down table 2-3 time at which i/os become active by ramp rate (at room temperature and nominal operating conditions) ramp rate 0.25v/ms 0.025v/ms 5v/ms 2.5v/ms 0.5v/ms 0.25v/ms 0.1v/ms 0.025v/ms units msmsmsmsmsmsmsms rtsx32su 10 100 0.46 0.74 2.8 5.2 12.1 47.2 rtsx72su 10 100 0.41 0.67 2.6 5.0 12.1 47.2
rtsx-su radtolerant fpgas (umc) 2-2 advanced v0.3 operating conditions absolute maximum conditions stresses beyond those listed in table 2-4 may cause permanent damage to the device. exposure to absolute maximum rated conditions may affect device reliability. devices should not be oper ated outside the recommendations in table 2- 5 . power dissipation a critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. the thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system's ability to dissipate heat. a complete power evaluation should be performed early in the design process to help identify potential heat- related problems in the system and to prevent the system from exceeding the device?s maximum allowed junction temperature. the actual power dissipated by most applications is significantly lower than the power the package can dissipate. however, a thermal analysis should be performed for all projects. to perform a power evaluation, follow these steps: 1. estimate the power consum ption of the application. 2. calculate the maximum power allowed for the device and package. 3. compare the estimated power and maximum power values. estimating power dissipation the total power dissipation for the rtsx-su family is the sum of the dc power dissipation and the ac power dissipation: p total = p dc + p ac eq 2-1 dc power dissipation the power due to standby cu rrent is typically a small component of the overa ll power. the dc power dissipation is defined as: p dc = (i cc )*v cca + (i cc )*v cci eq 2-2 table 2-4 absolute maximum conditions symbol parameter limits units v cci dc supply voltage ?0.3 to +6.0 v v cca dc supply voltage ?0.3 to +3.0 v v i input voltage ?0.5 to + 6.0 v v i input voltage for bidirectional i/os when using 3.3v pci ?0.5 to +v cci + 0.5 v t stg storage temperature ?65 to +150 c table 2-5 recommended operating conditions parameter military units temperature range (case temperature) ?55 to +125 c 2.5v power supply tolerance 2.25 to 2.75 v 3.3v power supply tolerance 3.0 to 3.6 v 5v power supply tolerance 4.5 to 5.5 v
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-3 ac power dissipation the power dissipation of the rtsx-su fa mily is usually dominated by the dyna mic power dissipation. dynamic power dissipation is a function of frequency, equivalent capacita nce, and power supply voltage. the ac power dissipation is defined as follows: eq 2-3 or: eq 2-4 where: guidelines for estimating power the following guidelines are meant to represent worst- case scenarios; they can be generally used to predict the upper limits of po wer dissipation: logic modules (m) = 20% of modules inputs switching (n) = # inputs/4 outputs switching (p) = # output/4 clka loads (q1) = 20% of r-cells clkb loads (q2) = 20% of r-cells load capacitance (cl) = 35 pf average logic module switching rate (fm) = f/10 average input switch ing rate (fn) =f/5 average output switching rate (fp) = f/10 average clka rate (fq1) = f/2 average clkb rate (fq2) = f/2 average hclk rate (fs1) = f hclk loads (s1) = 20% of r-cells to assist customers in estimating the power dissipations of their designs, actel has published the ex, sx-a and rt54sx-s power calculator worksheet. p ac = p c-cells + p r-cells + p clka + p clkb + p hclk + p output buffer + p input buffer p ac = v cca 2 * [(m * c eqcm * fm) c-cells + (m * c eqsm * fm) r-cells + (n * c eqi * f n ) input buffer + (p * (c eqo + c l ) * f p ) output buffer + (0.5 * (q 1 * c eqcr * f q1 ) + (r 1 * f q1 )) clka + (0.5 * (q 2 * c eqcr * f q2 )+ (r 2 * f q2 )) clkb + (0.5 * (s 1 * c eqhv * f s1 ) + (c eqhf * f s1 )) hclk ] c eqcm = equivalent capacitance of combinatorial modules (c-cells) in pf c eqsm = equivalent capacitance of sequential modules (r-cells) in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of clka/b in pf c eqhv = variable capacitance of hclk in pf c eqhf = fixed capacitance of hclk in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average clka rate in mhz f q2 = average clkb rate in mhz f s1 = average hclk rate in mhz m = number of logic modules switching at fm n = number of input buffers switching at fn p = number of output buffers switching at fp q 1 = number of clock loads on clka q 2 = number of clock loads on clkb r 1 = fixed capacitance due to clka r 2 = fixed capacitance due to clkb s 1 = number of clock loads on hclk x = number of i/os at logic low y = number of i/os at logic high table 2-6 fixed power parameters parameter rtsx32su rtsx72su units c eqcm 3.00 3.00 pf c eqsm 3.00 3.00 pf c eqi 1.40 1.30 pf c eqo 7.40 7.40 pf c eqcr 3.50 3.50 pf c eqhv 4.30 4.30 pf c eqhf 300 690 pf r 1 100 245 pf r 2 100 245 pf i cc 25 25 ma
rtsx-su radtolerant fpgas (umc) 2-4 advanced v0.3 thermal characteristics introduction the temperature variable in actel?s designer software refers to the junction te mperature, not the ambient, case, or board temperatur es. this is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient, case, or board temperatures. eq 2-5 , eq 2- 6 , and eq 2-7 give the relationship between thermal resistance, temperatur e gradient and power. eq 2-5 eq 2-6 eq 2-7 where: package thermal characteristics the device thermal characteristics jc and ja are given in table 2-7 . the thermal characteristics for ja are shown with two different air flow rates. note that the absolute maximum junction temperature is 150 c. maximum allowed power dissipation shown below are example calculations to estimate the maximum allowed power dissipation for a given device based on two different thermal environments while maintaining the device junction temperature at or below worst-case military operating conditions (125 c). example 1: this example assumes that there is still air in the en vironment. the heat flow is shown by the arrows in figure 2-1 on page 2-5 . the maximum ambient air temperature is assumed to be 50 c. the device package us ed is the 624-pin ccga. ja t j t a ? p ---------------- - = jc t j t c ? p ---------------- - = jb t j t b ? p ---------------- - = ja = junction-to-air thermal resistance of the package. ja numbers are located in ta b l e 2 - 7 . jc = junction-to-case therma l resistance of the package. jc numbers are located in ta b l e 2 - 7 . jb = junction-to-board thermal resistance of the package. jb for a 624-pin ccga is located in the notes for ta b l e 2 - 7 . t j = junction temperature t a = ambient temperature t b = board temperature t c = case temperature p = power table 2-7 package thermal characteristics package type pin count jc ja units still air ja 1.0m/s ja 2.5m/s ceramic quad flat pack (cqfp) 208 2.0 1 22 19.8 18.0 c/w ceramic quad flat pack (cqfp) 256 2.0 1 20 16.5 15.0 c/w ceramic quad flat pack (c qfp) with heatsink 208 0.5 1 21.0 17.3 15.7 c/w ceramic quad flat pack (c qfp) with heatsink 256 0.5 1 19.0 15.7 14.2 c/w ceramic chip carrier land grid (cclg) 256 1.1 1 12.1 10.0 9.1 c/w ceramic column grid array (ccga) 624 6.5 2 8.9 8.5 8.0 c/w notes: 1. jc for cqfp and cclg packages refers to the thermal resi stance between the junction and the bottom of the package. 2. jc for the ccga 624 refers to the thermal resistance between the junction and the top surface of the package. thermal resistance from junction to board ( jb ) for cg624 package is 3.4 c/w . max. allowed power max junction temp max. ambient temp ? ja -------------------- ----------------- ------------------ ------------------ ----------------- -------------- 125 c50 c ? 8.9 c/w ---------------- ------------------ - 8.43w ===
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-5 example 2: this example assumes that the primary heat conduction path will be through the bottom of the package (neglecting the heat conducted through the package pins) to the board for a package mounte d with thermal paste. the heat flow is shown by the arrows in figure 2-2 . the maximum board temperature is assumed to be 70 c. the device package used is the 352-pin cqfp. the thermal resistance ( cb ) of the thermal paste is assumed to be 0.58 c/w. timing derating rtsx-su devices are manufactured in a cmos process; therefore, device performance is dependent on temperature, voltage, and process variations. minimum timing paramete rs reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. the derating factors shown in table 2-8 should be applied to all timing data contained within this datasheet. figure 2-1 hear flow when air is present solder columns air pcb figure 2-2 heat flow in a vacuum table 2-8 temperature and voltage derating factors (normalized to worst-case military conditions, t j = 125c, v cca = 2.25v) v cca junction temperature (t j ) ?55c ?40c 0c 25c 70c 85c 125c 2.25 0.71 0.72 0.78 0.80 0.90 0.94 1.00 2.50 0.67 0.67 0.73 0.75 0.84 0.87 0.93 2.75 0.62 0.63 0.69 0.70 0.79 0.82 0.88 note: the user can set the junction temp erature in actel?s designer software to be any integer value in the range of ?55c to 175c, and the core voltage to be any value between 2.25v and 2.75v. max. allowed power t j t b ? jb ---------------- - t j t b ? jc cb + ------------ -------- - 125 c70 c ? 2.0 c/w 0.58 c/w + ------------------- ----------------- ----------------- - 21.32w == = = thermal adhesive pcb
rtsx-su radtolerant fpgas (umc) 2-6 advanced v0.3 timing model hardwired clock external setup = (t inyh + t rd2 + t sud ) ? t hckh = 0.7 + 1.0 + 0.8 ? 3.9 = ?1.4 ns clock-to-out (pad-to-pad) = t hckh + t rco + t rd1 + t dhl = 3.9 + 1.0 + 0.8 + 3.8 = 9.5 ns routed clock external setup = (t inyh + t rd2 + t sud ) ? t rckh = 0.7 + 1.0 + 0.8? 5.3= ?2.8 ns clock-to-out (pad-to-pad) = t rckh + t rco + t rd1 + t dhl = 5.3+ 1.0 + 0.8 + 3.8 = 10.9 ns figure 2-3 rtsx-su timing model values shown for rtsx32su, ?1, 0 krad (si) , 5v ttl worst-case military conditions input delays internal delays predicted routing delays output delays i/o module t inyh = 0.7 ns t rd2 = 1.0 ns t rd1 = 0.8 ns combinatorial cell i/o module t dhl = 3.8 ns t rd8 = 2.9 ns t rd4 = 1.5 ns t rd1 = 0.8 ns t pd = 1.2 ns i/o module t dhl = 3.8 ns t rd1 = 0.8 ns t rco = 1.0 ns i/o module t inyh = 0.7 ns t enzl = 2.5 ns t sud = 0.8 ns t hd = 0.0 ns t sud = 0.8 ns t hd = 0.0 ns t rckh = 5.3 ns (100% load) dq register cell routed clock t rd1 = 0.8 ns t rco = 1.0 ns t hckh = 3.9 ns dq register cell hardwired clock i/o module t dhl = 3.8 ns t enzl = 2.5 ns
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-7 i/o specifications pin descriptions supply pins gnd ground low supply voltage. v cci supply voltage supply voltage for i/os. see table 2-1 on page 2-1 . v cca supply voltage supply voltage for array. see table 2-1 on page 2-1 . global pins clka/b routed clock a and b these pins are clock inpu ts for clock distribution networks. input levels are co mpatible with standard ttl, lvttl, 3.3v pci, or 5v pci sp ecifications. the clock input is buffered prior to clocking the r-cells. when not used, this pin must be set low or high on the board. when used, this pin should be held low or high during power- up to avoid unwanted static power. for rtsx72su, these pins can be configured as user i/os. when used, this pin offers a built-in programmable pull- up or pull-down resistor active during power-up only. qclka/b/c/d quadrant cloc k a, b, c, and d / i/o these four pins are the quad rant clock inputs and are only found on the rtsx72su. they are clock inputs for clock distribution networks. input levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. the clock input is buffered prior to clocking the core cells. these pins can be configured as user i/os. when not used, these pins must not be left floating. they must be set low or high on the board. when used, these pins offer a built-in programmable pull-up or pull-down resistor, active during power-up only. hclk dedicated (hardwired) array clock this pin is the clock input for sequential modules. input levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. this input is buffered prior to clocking the r-cells. it offe rs clock speeds independent of the number of r-cells being driven. when not used, this pin must not be left floating. it must be set to low or high on the board. when used, this pin should be held low or high during power-up to avoid unwanted static power. jtag/probe pins pra/prb 1 , i/o probe a/b the probe pin is used to output data from any user- defined design node within the device. this independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. the probe pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. tck 1 , i/o test clock test clock input for diagnostic probe and device programming. in flexible mode, tck becomes active when the tms pin is set low ( table 2-32 on page 2-35 ). this pin functions as an i/o when the boundary scan state machine reaches the ?logic reset? state. tdi 1 , i/o test data input serial input for boundary scan testing and diagnostic probe. in flexible mode, tdi is active when the tms pin is set low ( table 2-32 on page 2-35 ). this pin functions as an i/o when the boundary sc an state machine reaches the ?logic reset? state. tdo 1 , i/o test data output serial output for boundary scan testing. in flexible mode, tdo is active when the tms pin is set low ( table 2-32 on page 2-35 ). this pin functions as an i/o when the boundary scan state machine reaches the "logic reset" state. when silicon explorer ii is being used, tdo will act as an output when the "checksum" command is run. it will return to user i/o when "checksum" is complete. tms 1 test mode select the tms pin controls th e use of the ieee 1149.1 boundary scan pins (tck, td i, tdo, trst). in flexible mode when the tms pin is set low, the tck, tdi, and tdo pins are boundary scan pins ( table 2-32 on page 2- 35 ). once the boundary scan pi ns are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the ?logic reset? state. at this point, the boundary scan pins will be released and will function as regular i/o pins. the ?logic reset? state is reached five tck cycles afte r the tms pin is set high. in dedicated test mode, tms functions as specified in the ieee 1149.1 specifications. 1. these pins should be terminated with a 70 ? resistor to preserve probing capabilities.
rtsx-su radtolerant fpgas (umc) 2-8 advanced v0.3 trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize or rest the boundary scan circuit. the trst pin is equipped with an internal pull-up resistor. for flight applicat ions, the trst pin should be hardwired to gnd. user i/o i/o input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. input and output levels are compatible with standard ttl, lvttl, 3.3v/5v pci, or 5v cmos specifications. unused i/o pins are automatically tristated by the design er software. see the "user i/o" section on page 2-8 for more details. special functions nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. user i/o the rtsx-su family features a flexible i/o structure that supports 3.3v lvttl, 5v ttl, 5v cmos, and 3.3v and 5v pci. all i/o standards are hot-swap compliant, cold- sparing capable, and 5v tole rant (except for 3.3v pci). each i/o module has an available power-up resistor of approximately 50 k ? that can configure the i/o to a known state during power-up. just slightly before v cca reaches 2.5v, the resistors are disabled so the i/os will behave normally. for more information about the power-up resistors, please see actel?s application note sx-a and rtsx-s devices in hot-swap and cold sparing applications . rtsx-su inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. if the input voltage is greater than v cci and a fast push-pull device is not used, the high-resistance pull-up of the driver and the internal circuitry of the rtsx-su i/o may create a voltage divider (when a user i/o is configured as an input, the associated output buffer is tristated). this voltage divider could pull the input voltage below specification for some devices connected to the driver. a logic ?1? may not be correctly presented in this case. for example, if an open drain dr iver is used with a pull-up resistor to 5v to provide the logic ?1? input, and v cci is set to 3.3v on the rtsx-su device, the input signal may be pulled down by the rtsx-su input. hot swapping rtsx-su i/os can be configured to be hot swappable in compliance with the comp act pci specification. however, a 3.3v pci device is not hot swappable. during power-up/down, all i/os are tristated. v cca and v cci do not have to be stable during power-up/down. after the rtsx-su device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. the device?s output pins are driven to a high impedance state until normal chip operating condit ions are reached. table 2-3 on page 2-1 summarizes the v cca voltage at which the i/os behave according to the user?s design for an rtsx-su device at room temperature for various ramp-up rates. the data reported assumes a linear ramp-up profile to 2.5v. refer to actel?s application note, sx-a and rtsx-s devices in hot-swap and cold-sparing applications for more information on hot swapping. customizing the i/o each user i/o on an rtsx-su device can be configured as an input, an output, a tristate output, or a bidirectional pin. mixed i/o standards are allowed and can be set on a pin-by-pin basis. high or low slew rates can be set on individual output buffers (except for pci which defaults to high slew), as well as the power-up configuration (either pull-up or pull-down). the user selects the desired i/o by setting the i/o properties in pineditor, actel?s graphical pin-placement and i/o properties editor. see the pineditor online help for more information. unused i/os all unused user i/os are automatically tristated by actel?s designer software. although termination is not required, it is recommended that the user tie off all unused i/os to gnd externally. if the i/o clamp diode is disabled, then unused i/os are 5v tolerant, otherwise unused i/os are tolerant to v cci .
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-9 i/o macros there are nine i/o macros available to the user for rtsx-su: clkbuf/clkbufi: clock buffer, noninverting and inverting clkbibuf/clkbibufi: bidirectional clock buffer, noninverting and inverting qclkbuf/qclkbufi: quad clock buffer, noninverting and inverting qclkbibuf/qclkbibufi: quad bidirectional clock buffer, noninverting and inverting hclkbuf: hardwired clock buffer inbuf: input buffer outbuf: output buffer tribuf: tristate buffer bibuf: bidirectional buffer table 2-9 user i/o features function description input buffer threshold selections 5v: cmos, pci, ttl 3.3v: pci, lvttl flexible output driver 5v: cmos, pci, ttl 3.3v: pci, lvttl selectable on an individual i/o basis output buffer ?hot-swap? capability i/os on an unpowered device does not si nk the current (power supplies are at 0v) can be used for ?cold sparing? individually selectable slew rate, high or low sl ew (the default is high slew rate). the slew rate selection only affects the falling edge of an output. there is no change on the rising edge of the output or any inputs power-up individually selectable pull-ups and pull- downs during power-up (default is to power-up in tristate mode) enables deterministic power-up of a device v cca and v cci can be powered in any order
rtsx-su radtolerant fpgas (umc) 2-10 advanced v0.3 i/o module timing c haracteristics figure 2-4 output timing model and waveforms figure 2-5 input timing model and waveforms figure 2-6 ac test loads to ac test loads (shown below) pa d d e tr ibu ff d v cc gnd 50% pad v ol v oh t dlh 50% t dhl e v cc gnd 50% pad v ol t enzl 50% 10% t enlz e v cc gnd 50% vpad gnd v oh t enzh 50% 90% t en hz v cc v meas v meas v meas v meas pa d y inbuf pad 0v y gnd v cc 50% 50% t inyh t inyl v meas v meas v cci lo ad 1 (used to measure load 2 (used to measure enable delays) 35 pf to the output v cc gnd 35 pf to the output r to v cc for t pzl r to gnd for t pzh r = 1 k ? propagation delay) under test under test load 3 (used to measure disable delays) 5 pf to the output r to v cc for t plz r to gnd for t phz r = 1 k ? under test v cc gnd
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-11 5v ttl and 3.3v lvttl table 2-10 5v ttl and 3.3v lvttl electrical specifications symbol military parameter min. max. units v oh v cci = min. v i = v ih or v il (i oh = -1ma) 0.9 v cci v v cci = min. v i = v ih or v il (i oh = -8ma) 2.4 v v ol v cci = min. v i = v ih or v il (i ol = 1ma) 0.1 v cci v v cci = min. v i = v ih or v il (i ol = 12ma) 0.4 v v il input low voltage 0.8 v v ih input high voltage 2.0 v i il / i ih input leakage current, v in = v cci or gnd (v cci 5.25v) (v cci 5.5v) ?20 ?70 20 70 a a i oz tristate output leakage current, v out = v cci or gnd (v cci 5.25v) (v cci 5.5v) ?20 ?70 20 70 a a t r , t f input transition time 10 ns c in input pin capacitance 3 20 pf c clk clk pin capacitance 3 20 pf v meas trip point for input buffers and measuring point for output buffers 1.5 v iv curve 2 can be derived from the ibis model on the web. notes: 1. the ibis model can be found at www.actel.com/techdocs/models/ibis.html . 2. if t r /t f exceeds the limit of 10 ns, actel can guarantee reliability but not functionality. 3. absolute maximum pin capacitance, which includes package and i/o input capacitance.
rtsx-su radtolerant fpgas (umc) 2-12 advanced v0.3 timing characteristics table 2-11 rtsx32su 5v ttl and 3.3v lvttl i/o module worst-case military conditions v cca = 2.25v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v ttl output module timing (v cci = 4.5v) t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 3.1 3.6 ns t dhl data-to-pad high to low 3.8 4.4 ns t dhls data-to-pad high to low ? low slew 9.8 11.5 ns t enzl enable-to-pad, z to low 2.5 3.0 ns t denzls enable-to-pad, z to low ? low slew 9.0 10.6 ns t enzh enable-to-pad, z to high 3.1 3.6 ns t enlz enable-to-pad, low to z 4.4 5.3 ns t enhz enable-to-pad, high to z 3.8 4.4 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf d thls delta delay vs. load high to low ? low slew 0.049 0.064 ns/pf 3.3v lvttl output module timing (v cci = 3.0v) t inyh input data pad-to-y high 0.8 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 4.1 4.8 ns t dhl data-to-pad high to low 3.7 4.4 ns t dhls data-to-pad high to low ? low slew 13.2 15.6 ns t enzl enable-to-pad, z to l 2.9 3.4 ns t denzls enable-to-pad, z to low ? low slew 12.7 14.9 ns t enzh enable-to-pad, z to h 4.1 4.8 ns t enlz enable-to-pad, l to z 3.7 4.4 ns t enhz enable-to-pad, h to z 3.7 4.4 ns d tlh delta delay vs. load low to high 0.064 0.081 ns/pf d thl delta delay vs. load high to low 0.031 0.040 ns/pf d thls delta delay vs. load high to low ? low slew 0.069 0.088 ns/pf note: output delays based on 35 pf loading.
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-13 table 2-12 rtsx72su 5v ttl and 3.3v lvttl i/o module worst-case military conditions v cca = 2.25v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v ttl output module timing (v cci = 4.5v) t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 3.2 3.7 ns t dhl data-to-pad high to low 4.0 4.7 ns t dhls data-to-pad high to low ? low slew 10.3 12.1 ns t enzl enable-to-pad, z to low 2.5 3.0 ns t denzls enable-to-pad, z to low ? low slew 9.0 10.6 ns t enzh enable-to-pad, z to high 3.2 3.7 ns t enlz enable-to-pad, low to z 4.4 5.3 ns t enhz enable-to-pad, high to z 4.0 4.7 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf d thls delta delay vs. load high to low ? low slew 0.049 0.064 ns/pf 3.3v lvttl output module timing (v cci = 3.0v) t inyh input data pad-to-y high 1.0 1.2 ns t inyl input data pad-to-y low 2.2 2.5 ns t dlh data-to-pad low to high 4.0 4.6 ns t dhl data-to-pad high to low 3.6 4.2 ns t dhls data-to-pad high to low ? low slew 12.7 14.9 ns t enzl enable-to-pad, z to l 2.9 3.4 ns t denzls enable-to-pad, z to low ? low slew 12.7 14.9 ns t enzh enable-to-pad, z to h 4.0 4.6 ns t enlz enable-to-pad, l to z 3.9 4.4 ns t enhz enable-to-pad, h to z 3.6 4.2 ns d tlh delta delay vs. load low to high 0.064 0.081 ns/pf d thl delta delay vs. load high to low 0.031 0.04 ns/pf d thls delta delay vs. load high to low ? low slew 0.069 0.088 ns/pf note: output delays based on 35 pf loading.
rtsx-su radtolerant fpgas (umc) 2-14 advanced v0.3 5v cmos timing characteristics table 2-13 5v cmos electrical specifications symbol military parameter min. max. units v oh v cci = min, v i = v cci or gnd (i oh = ?20 a) v cci - 0.1 v v ol v cci = min, v i = v cci or gnd (i ol = 20 a) 0.1 v v il input low voltage, v out = v vol(max) 0.3v cc v v ih input high voltage, v out = v voh(min) 0.7v cc v i oz tristate output leakage current, v out = v cci or gnd (v cci 5.25v) (v cci 5.5v) ?20 ?70 20 70 a a t r , t f input transition time 10 ns c in input pin capacitance 1 20 pf c clk clk pin capacitance 1 20 pf v meas trip point for input buffers and measuring point for output buffers 2.5 v iv curve can be derived from the ibis model on the web. 2 notes: 1. absolute maximum pin capacitance, which includes package and i/o input capacitance. 2. the ibis model can be found at www.actel.com/techdocs/models/ibis.html . table 2-14 rtsx32su 5v cmos i/o module worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v cmos output module timing t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 3.4 4.0 ns t dhl data-to-pad high to low 3.6 4.2 ns t dhls data-to-pad high to low ? low slew 8.7 10.3 ns t enzl enable-to-pad, z to low 2.3 2.8 ns t denzls enable-to-pad, z to low ? low slew 8.8 10.4 ns t enzh enable-to-pad, z to high 3.6 4.2 ns t enlz enable-to-pad, low to z 4.5 5.3 ns t enhz enable-to-pad, high to z 3.4 4.0 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf d thls delta delay vs. load high to low ? low slew 0.049 0.064 ns/pf note: output delays based on 35 pf loading.
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-15 table 2-15 rtsx72su 5v cmos i/o module worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v cmos output module timing t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 0.0 0.0 ns t dlh data-to-pad low to high 3.6 4.2 ns t dhl data-to-pad high to low 3.8 4.5 ns t dhls data-to-pad high to low ? low slew 9.2 10.8 ns t enzl enable-to-pad, z to low 2.3 2.8 ns t denzls enable-to-pad, z to low ? low slew 8.8 10.4 ns t enzh enable-to-pad, z to high 3.8 4.5 ns t enlz enable-to-pad, low to z 4.5 5.3 ns t enhz enable-to-pad, high to z 3.6 4.2 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf d thls delta delay vs. load high to low ? low slew 0.049 0.064 ns/pf note: output delays based on 35 pf loading.
rtsx-su radtolerant fpgas (umc) 2-16 advanced v0.3 5v pci the rtsx-su family supports 5v pci and is compliant with the pci lo cal bus specification rev. 2.1. equation a i oh = 11.9 * (v out ? 5.25) * (v out + 2.45) for v cci > v out > 3.1v equation b i ol = 78.5 * v out * (4.4 ? v out ) for 0v < v out < 0.71v table 2-16 5v pci dc specifications symbol parameter condition min. max. units v cca supply voltage for array 2.25 2.75 v v cci supply voltage for i/os 4.5 5.5 v v ih input high voltage 1 2.0 v cci + 0.5 v v il input low voltage 1 ?0.5 0.8 v i ih input high leakage current v in = 2.75 70 a i il input low leakage current v in = 0.5 ?70 a v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage 2 i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf v meas trip point for input buffers and measuring point for output buffers 1.5 v notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 2. signals without pull-up resistors must have 3 ma low output current. signals requiring pull-up must have 6 ma; the latter inc lude, frame#, irdy#, trdy#, devsel#, stop#, serr#, perr#, lock#, and, when used ad[63::32], c/be[7::4]#, par64, req64#, and ack64#. 3. absolute maximum pin capacitance for a pci input is 10 pf (exc ept for clk) with an exception granted to motherboard-only devi ces, which could be up to 16 pf in order to accommodate pga packaging. this mean that components fo r expansion boards need to use alternatives to ceramic pga packag ing (i.e., pbga,pqfp, sga, etc.). figure 2-7 5v pci v/i curve for rtsx-su ?200.0 ?150.0 ?100.0 ?50.0 0.0 50.0 100.0 150.0 200.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 voltage out (v) current (ma) i oh i ol i oh min. specification i oh max. specification i ol min. specification i ol max. specification
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-17 table 2-17 5v pci ac specifications symbol parameter condition min. max. units i oh(ac) 0 < v out < 1.4 1 ?44 ma switching current high 1.4 < v out < 2.4 1, 2 (?44 + (v out ? 1.4)/0.024) ma 3.1 < v out < v cci 1, 3 "equation a" on page 2-16 (test point) v out = 3.1 3 ?142 ma i ol(ac) v out = 2.2 1 95 ma switching current low 2.2 > v out > 0.55 1 (v out /0.023) ma 0.71 > v out > 0 1, 3 "equation b" on page 2-16 (test point) v out = 0.71 206 ma i cl low clamp current ?5 < v in ?1 ?25 + (v in + 1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 4 15v/ns slew f output fall slew rate 2.4v to 0.4v load 4 15v/ns notes: 1. refer to the v/i curves in figure 2-7 on page 2-16 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half si ze output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. the ?switchi ng current high? specificatio n is not relevant to serr#, inta#, intb#, intc#, and intd#, which are open drain outputs. 2. note that this segment of the minimum cu rrent curve is drawn from the ac drive point directly to the dc drive point rather th an toward the voltage rail (as is done in th e pull-down curve). this difference is intended to allow for an optional n-channel pul l-up. 3. maximum current requirements must be met as drivers pull bey ond the last step voltage. equations defining these maximums (a and b) are provided with the respective curves in figure 2-7 on page 2-16 . the equation defined maximum should be met by the design. in order to facilitate component testing, a maximum curre nt test point is defined for eac h side of the output driver. 4. this parameter is to be interpreted as th e cumulative edge rate across the specifie d range, rather than the instantaneous rat e at any point within the transition range. the specified load is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the pci local bus specification ( figure 2-8 ). however, adherence to both the maximum and minimum parameters is now required (the maximum is no longer simply a guideline). since adhe rence to the maximum slew rate was not required prior to revision 2.1 of the specification, ther e may be components in the market that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and shou ld ensure that signal integrity modeling accounts for this. rise slew rate does not apply to open drain outputs. figure 2-8 5v pci output loading pin output buffer 50 pf
rtsx-su radtolerant fpgas (umc) 2-18 advanced v0.3 timing characteristics table 2-18 rtsx32su 5v pci i/o module worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v pci output module timing t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 3.4 4.0 ns t dhl data-to-pad high to low 4.1 4.8 ns t enzl enable-to-pad, z to low 2.8 3.3 ns t enzh enable-to-pad, z to high 3.4 4.0 ns t enlz enable-to-pad, low to z 4.9 5.8 ns t enhz enable-to-pad, high to z 4.1 4.8 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf note: output delays based on 50 pf loading. table 2-19 rtsx72su 5v pci i/o module worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 5v pci output module timing t inyh input data pad-to-y high 0.7 0.9 ns t inyl input data pad-to-y low 1.1 1.3 ns t dlh data-to-pad low to high 3.5 4.1 ns t dhl data-to-pad high to low 4.3 5.1 ns t enzl enable-to-pad, z to low 2.8 3.3 ns t enzh enable-to-pad, z to high 3.5 4.1 ns t enlz enable-to-pad, low to z 4.9 5.8 ns t enhz enable-to-pad, high to z 4.3 5.1 ns d tlh delta delay vs. load low to high 0.036 0.046 ns/pf d thl delta delay vs. load high to low 0.029 0.038 ns/pf note: output delays based on 50 pf loading.
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-19 3.3v pci the rtsx-su family supports 3.3v pc i and is compliant with the pci lo cal bus specification rev. 2.1. equation c i oh = (98.0/v cci ) * (v out ? v cci ) * (v out + 0.4v cci ) for v cci > v out > 0.7 v cci equation d i ol = (256/v cci ) * v out * (v cci ? v out ) for 0v < v out < 0.18 v cci table 2-20 3.3 v pci dc specifications symbol parameter condition min. max. units v cca supply voltage for array 2.25 2.75 v v cci supply voltage for i/os 3.0 3.6 v v ih input high voltage 0.5v cci v cci + 0.5 v v il input low voltage ?0.5 0.3v cci v i ipu input pull-up voltage 1 0.7v cci v i il /i ih input leakage current 2 0 < v in < v cci 20 a v oh output high voltage i out = ?500 a 0.9v cci v v ol output low voltage i out = 1500 a 0.1v cci v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf v meas trip point for input buffers 0.4 * v cci v output buffer measuring point - rising edge 0.285 * v cci output buffer measuring point - falling edge 0.615 * v cci notes: 1. this specification should be guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pul l a floated network. applications sensitive to static power utiliz ation should assure that the input buffer is conducting minimum c urrent at this input v in . 2. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 3. absolute maximum pin capacitance for a pci input is 10 pf (e xcept for clk) with an except ion granted to motherboard-only devices, which could be up to 16 pf, in order to accommodate pga packaging. this means that components for expansion boards would need to use alternatives to ceramic pga packaging. figure 2-9 3.3v pci v/i curve for the rtsx-su family ?150.0 ?100.0 ?50.0 0.0 50.0 100.0 150.0 0 0.5 1 1.5 2 2.5 3 3.5 4 voltage out (v) current (ma) i oh i ol i oh min. specification i oh max. specification i ol min. specification i ol max. specification
rtsx-su radtolerant fpgas (umc) 2-20 advanced v0.3 table 2-21 3.3v pci ac specifications symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 0.3v cci 1 ?12v cci ma 0.3v cci v out < 0.9v cci 1 (?17.1 + (v cci ? v out )) ma 0.7v cci < v out < v cci 1, 2 "equation c" on page 2-19 (test point) v out = 0.7v cc 2 ?32v cci ma i ol(ac) switching current low v cci > v out 0.6v cci 1 16v cci ma 0.6v cci > v out > 0.1v cci 1 (26.7v out) ma 0.18v cci > v out > 0 1, 2 "equation d" on page 2-19 (test point) v out = 0.18v cc 2 38v cci ma i cl low clamp current ?3 < v in ?1 ?25 + (v in + 1)/0.015 ma i ch high clamp current v cci + 4 > v in v cci + 1 25 + (v in ? v cci ? 1)/0.015 ma slew r output rise slew rate 0.2v cci to 0.6v cci load 3 14v/ns slew f output fall slew rate 0.6v cci to 0.2v cci load 3 14v/ns notes: 1. refer to the v/i curves in figure 2-9 on page 2-19 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half-siz e output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. the ?switc hing current high? specification is not rele vant to serr#, inta#, intb#, intc#, and intd#, which are open drain outputs. 2. maximum current requireme nts must be met as drivers pull beyond the last st ep voltage. equations defining these maximums (c and d) are provided with the respective curves in figure 2-9 on page 2-19 . the equation defined maximum should be met by the design. in order to facilitate component testing, a maximum curre nt test point is defined for eac h side of the output driver. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, ra ther than the instantaneous rat e at any point within the transition range. the specified load is optional ( figure 2-10 ); i.e., the designer may elec t to meet this parameter with an unloaded output per the latest revision of the pci lo cal bus specification. however, adherence to both maximum and minimum parameters is required (the maximu m is no longer simply a guideline). rise slew rate does not apply to open drain outputs. figure 2-10 3.3v pci outp ut loading pin output buffer 1 k/25 ? 1/2 in. max. 10 pf pin output buffer 1 k/25 ? 1/2 in. max. 10 pf v c c
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-21 timing characteristics table 2-22 rtsx32su 3.3v pci i/o module worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 3.3v pci output module timing t inyh input data pad-to-y high 0.8 0.9 ns t inyl input data pad-to-y low 0.9 1.1 ns t dlh data-to-pad low to high 3.0 3.5 ns t dhl data-to-pad high to low 3.0 3.5 ns t enzl enable-to-pad, z to low 2.1 2.5 ns t enzh enable-to-pad, z to high 3.0 3.5 ns t enlz enable-to-pad, low to z 2.7 3.9 ns t enhz enable-to-pad, high to z 3.0 3.5 ns d tlh delta delay vs. load low to high 0.067 0.085 ns/pf d thl delta delay vs. load high to low 0.031 0.040 ns/pf note: delays based on 10 pf loading and 25 ? resistance. table 2-23 rtsx72su 3.3v pci i/o module worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. 3.3v pci output module timing t inyh input data pad-to-y high 0.7 0.8 ns t inyl input data pad-to-y low 0.9 1.1 ns t dlh data-to-pad low to high 2.8 3.3 ns t dhl data-to-pad high to low 2.8 3.3 ns t enzl enable-to-pad, z to low 2.1 2.5 ns t enzh enable-to-pad, z to high 2.8 3.3 ns t enlz enable-to-pad, low to z 2.7 3.9 ns t enhz enable-to-pad, high to z 2.8 3.3 ns d tlh delta delay vs. load low to high 0.067 0.085 ns/pf d thl delta delay vs. load high to low 0.031 0.040 ns/pf note: delays based on 10 pf loading and 25 ? resistance.
rtsx-su radtolerant fpgas (umc) 2-22 advanced v0.3 module specifications c-cell introduction the c-cell is one of the two logic module types in the rtsx-su architecture. it is the combinatorial logic resource in the device. the rt sx-su architecture uses the same c-cell configuration as found in the sx and sx-a families. the c-cell features the following ( figure 2-11 ): eight-input mux (data: d0 -d3, select: a0, a1, b0, b1). user signals can be routed to any one of these inputs. c-cell inputs (a0, a1, b0, b1) can be tied to one of the either the routed or quad clocks (clka/b or qclka/b/c/d). inverter (db input) can be used to drive a complement signal of any of the inputs to the c-cell. a hardwired connection (direct connect) to the associated r-cell with a si gnal propagation time of less than 0.1 ns. this layout of the c-cell enables the implementation of over 4,000 functions of up to five bits. for example, two c-cells can be used together to implement a four-input xor function in a single cell delay. the c-cell configuration is ha ndled automatically for the user with actel's extensive macro library (please see actel?s antifuse macro library guide for a complete listing of available rtsx-s macros). figure 2-11 c-cell figure 2-12 c-cell timing model and waveforms d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y s a b y s, a or b y gnd v cc 50% t pd y gnd gnd v cc 50% 50% 50% v cc 50% 50% t pd t pd t pd
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-23 timing characteristics r-cell introduction the r-cell, the sequential logic resource of rtsx-su devices, is the second logic module type in the rtsx-su family architecture. the rtsx-su r-cell is an seu- enhanced version of the sx and sx-a r-cell ( figure 2-13 ). the main features of the r-cell include the following: direct connection to the adjacent c-cell through the hardwired connection dcin. dcin is driven by the dcout of an adjacent c-cell via the direct- connect routing resource, providing a connection with less than 0.1 ns of routing delay. the r-cell can be used as a standalone flip-flop. it can be driven by any ot her c-cell or i/o modules through the regular routing structure (using din as a routable data input). this gives the option of using it as a 2:1 mu xed flip-flop as well. independent active-low as ynchronous clear (clrb). independent active-low asynchronous preset (psetb). if both clrb and psetb are low, clrb has higher priority. clock can be driven by any of the following (ckp input selects clock polarity): ? the high-performance, hardwired, fast clock (hclk) ? one of the two routed clocks (clka/b) ? one of the four quad clocks (qclka/b/c/d) in the case of the rtsx72su ? user signals s0, s1, psetb, and clrb can be driven by clka/b, qclka/b/c/d (for the rtsx72su) or user signals. routed data input and s1 can be driven by user signals. as with the c-cell, the conf iguration of the r-cell to perform various functions is handled automatically for the user through actel's extensive macro library (please see actel?s macro library guide for a complete listing of available rtsx-s macros). table 2-24 c-cell worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. c-cell propagation delays t pd internal array module 1.2 1.4 ns note: for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. figure 2-13 r-cell direct connect input clka, clkb, internal logic hclk cks ckp clrb psetb y dq routed data input s0 s1
rtsx-su radtolerant fpgas (umc) 2-24 advanced v0.3 seu-hardened d flip-flop in order to meet the stringent seu requirements of a let threshold greater than 40mev-cm 2 /gm, the internal design of the r-cell was modified without changing the functionality of the cell. figure 2-14 is a simplified representation of how the d flip-flop in the r-cell is implemented in the sx-a architecture. the flip-flop cons ists of a master and a slave latch gated by opposite edges of the clock. each latch is constructed by feeding back the output to the input stage. the potential problem in a space environment is that either of the latches ca n change state when hit by a particle with enough energy. to achieve the seu requiremen ts, the d flip-flop in the rtsx-su r-cell is enhanced ( figure 2-15 ). both the master and slave "latches" are each implemented with three latches. the asynchronous se lf-correcting feedback paths of each of the three latches is voted with the outputs of the other two latches. if one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. care was taken in the layout to ensure that a sing le ion strike could not affect more than one latch. figure 2-16 shows a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip- flop. the inputs to each of the three latches are independently controllable so the voting circuitry in the asynchronous self-correcting feedback paths can be tested exhaustively. this testing is performed on an unprogrammed array during wafer sort, final test, and post-burn-in test. this test circuitry cannot be used to test the flip-flops once the device has been programmed. figure 2-14 sx-a r-cell implementation of a d flip-flop figure 2-15 rtsx-su r-cell implementation of d flip-flop using voter gate logic d clk clk q clk clk d clk q voter gate clk clk clk clk clk
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-25 figure 2-16 r-cell implementation ? test circuitry figure 2-17 r-cell timing models and waveforms tst1 clk d q voter gate tst2 tst3 test circuitry (positive edge triggered) d clk clr q d clk q clr t hpwh rco t wasyn t sud t hpwl t t clr t rpwl t rpwh preset t preset pre t hd t hp
rtsx-su radtolerant fpgas (umc) 2-26 advanced v0.3 timing characteristics table 2-25 r-cell worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. r-cell propagation delays t rco sequential clock-to-q 1.0 1.2 ns t clr asynchronous clear-to-q 0.8 1.0 ns t preset asynchronous preset-to-q 1.1 1.3 ns t sud flip-flop data input set-up 0.8 1.0 ns t hd flip-flop data input hold 0.0 0.0 ns t wasyn asynchronous pulse width 2.8 3.3 ns t recasyn asynchronous recovery time 0.7 0.8 ns t hasyn asynchronous hold time 0.7 0.8 ns
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-27 routing specifications routing resources the routing structure found in rtsx-su devices enables any logic module to be connected to any other logic module in the device while retaining high performance. there are multiple paths and routing resources that can be used to route one logic module to another, both within a supercluster and elsewhere on the chip. there are three primary type s of routing within the rtsx-su architecture: directconnect, fastconnect, and vertical and horizontal routing. directconnect directconnects provide a high-speed connection between an r-cell and its adjacent c-cell ( figure 1-3 and figure 1-4 on page 1-4 ). this connection can be made from the y output of the c-cell to the di rectconnect input of the r-cell by configuring of the s0 line of the r-cell. this provides a connection that do es not require an antifuse and has a delay of less than 0.1 ns. fastconnect for high-speed routing of logic signals, fastconnects can be used to build a short distance connection using a single antifuse ( figure 1-3 and figure 1-4 on page 1-4 ). fastconnects provide a maximum delay of 0.4 ns. the outputs of each logic module connect directly to the output tracks within a supercluster. signals on the output tracks can then be routed through a single antifuse connection to drive the inputs of logic modules either within one superclust er or in the supercluster immediately below. horizontal and vertical routing in addition to directconnect and fastconnect, the architecture makes use of tw o globally-oriented routing resources known as segmented routing and high-drive routing. actel?s segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic plac e-and-route software to minimize signal propagation delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for the initial design performance evaluation. critical net delays can then be applied to the most time-critical paths. critical nets are determined by net property assignment prior to placement and routing. up to six percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. long tracks some nets in the design use long tracks. long tracks are special routing resources th at span multiple rows, columns, or modules. long tracks employ three and sometimes five antifuse connections. this increases capacitance and resistance results in longer net delays for macros connected to long tracks. typically up to six percent of nets in a fully utilized device require long tracks. long tracks can cause a delay from 4.0 ns to 8.4 ns. this additional delay is represented statistically in higher fanout routing delays in the "timing characteristics" section on page 2-28 .
rtsx-su radtolerant fpgas (umc) 2-28 advanced v0.3 timing characteristics table 2-26 rtsx32su worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. predicted routing delays t dc fo=1 routing delay, directconnect 0.1 0.1 ns t fc fo=1 routing delay, fastconnect 0.4 0.4 ns t rd1 fo=1 routing delay 0.8 0.9 ns t rd2 fo=2 routing delay 1.0 1.2 ns t rd3 fo=3 routing delay 1.4 1.6 ns t rd4 fo=4 routing delay 1.5 1.8 ns t rd8 fo=8 routing delay 2.9 3.4 ns t rd12 fo=12 routing delay 4.0 4.7 ns note: routing delays are for typical designs acro ss worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. table 2-27 rtsx72su worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. predicted routing delays t dc fo=1 routing delay, directconnect 0.1 0.1 ns t fc fo=1 routing delay, fastconnect 0.4 0.4 ns t rd1 fo=1 routing delay 0.9 1.0 ns t rd2 fo=2 routing delay 1.2 1.4 ns t rd3 fo=3 routing delay 1.8 2.0 ns t rd4 fo=4 routing delay 1.9 2.3 ns t rd8 fo=8 routing delay 3.7 4.3 ns t rd12 fo=12 routing delay 5.1 6.0 ns note: routing delays are for typical designs acro ss worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance.
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-29 global resources one of the most important aspects of any fpga architecture is its global resource or clock structure. the rtsx-su family provides flex ible and easy-to-use global resources without the limit ations normally found in other fpga architectures. the rtsx-su architecture cont ains three types of global resources, the hclk (hardwired clock) and clk (routed clock) and in the rtsx72su, qclk (quadrant clock). each rtsx-su device is provided with one hclk and two clks. the rtsx72su has an additional four qclks. hardwired clock the hardwired (hclk) is a low-skew network that can directly drive the clock inputs of all r-cells in the device with no antifuse in the path. the hclk is available everywhere on the chip. upon power-up of the rtsx-su device, four clock pulses must be detected on hclk be fore the clock signal will be propagated to registers in the device. routed clocks the routed clocks (clk a and clkb) are low-skew networks that can drive the clock inputs of all r-cells in the device (logically equivalent to the hclk). clk has the added flexibility in that it can drive the s0 (enable), s1, psetb, and clrb inputs of r-cells as well as any of the inputs of any c-cell in the de vice. this allows clks to be used not only as clocks but also for other global signals or high fanout nets. both clks are available everywhere on the chip. if clka or clkb pins are not used or sourced from signals, then these pins must be set as low or high on the board. they must not be left floating (except in rtsx72su, where these cloc ks can be configured as regular i/os). quadrant clocks the rtsx72su device provides four quadrant clocks (qclka, qclkb, qclkc, qclk d) to the user, which can be sourced from external pins or from internal logic signals within the device. each of these clocks can individually drive up to one full quadrant of the chip, or they can be grouped together to drive multiple quadrants ( figure 2-18 ). if qclks are not used as quadrant clocks, they can behave as regular i/os. see actel?s application note using a54sx72a and rt54sx72s quadrant clocks for more information. figure 2-18 rtsx-su qclk structure 4 4 4 qclkbufs qclkint (to array) qclkint (to array) qclkint (to array) qclkint (to array) 5:1 5:1 5:1 5:1 quadrant 2 quadrant 0 quadrant 3 quadrant 1
rtsx-su radtolerant fpgas (umc) 2-30 advanced v0.3 timing characteristics table 2-28 rtsx32su at v cci = 3.0v worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. dedicated (hardwired) array clock network t hckh pad to r-cell input low to high 3.9 4.6 ns t hckl pad to r-cell input high to low 3.9 4.6 ns t hpwh minimum pulse width high 2.1 2.5 ns t hpwl minimum pulse width low 2.1 2.5 ns t hcksw maximum skew 1.6 1.9 ns t hp minimum period 4.2 5.0 ns f hmax maximum frequency 238 200 mhz routed array clock networks t rckh pad to r-cell input high to low (light load)) 4.2 4.9 ns t rchkl pad to r-cell input low to high (light load)) 3.9 4.6 ns t rckh pad to r-cell input low to high (50% load) 5.0 5.9 ns t rckl pad to r-cell input high to low (50% load) 4.3 5.1 ns t rckh pad to r-cell input low to high (100% load) 5.6 6.5 ns t rckl pad to r-cell input high to low (100% load) 4.9 5.7 ns t rpwh minimum pulse width high 2.1 2.5 ns t rpwl minimum pulse width low 2.1 2.5 ns t rcksw maximum skew (light load) 2.8 3.3 ns t rcksw maximum skew (50% load) 2.8 3.3 ns t rcksw maximum skew (100% load) 2.8 3.3 ns t rp minimum period 4.2 5.0 ns f rmax maximum frequency 238 200 mhz
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-31 table 2-29 rtsx32su at v cci = 4.5v worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. dedicated (hardwired) array clock network t hckh pad to r-cell input low to high 3.9 4.6 ns t hckl pad to r-cell input high to low 3.9 4.6 ns t hpwh minimum pulse width high 2.1 2.5 ns t hpwl minimum pulse width low 2.1 2.5 ns t hcksw maximum skew 1.6 1.9 ns t hp minimum period 4.2 5.0 ns f hmax maximum frequency 238 200 mhz routed array clock networks t rckh pad to r-cell input high to low (light load)) 3.9 4.6 ns t rchkl pad to r-cell input low to high (light load)) 3.7 4.4 ns t rckh pad to r-cell input low to high (50% load) 4.7 5.6 ns t rckl pad to r-cell input high to low (50% load) 4.1 4.9 ns t rckh pad to r-cell input low to high (100% load) 5.3 6.2 ns t rckl pad to r-cell input high to low (100% load) 4.7 5.5 ns t rpwh minimum pulse width high 2.1 2.5 ns t rpwl minimum pulse width low 2.1 2.5 ns t rcksw maximum skew (light load) 2.8 3.3 ns t rcksw maximum skew (50% load) 2.8 3.3 ns t rcksw maximum skew (100% load) 2.8 3.3 ns t rp minimum period 4.2 5.0 ns f rmax maximum frequency 238 200 mhz
rtsx-su radtolerant fpgas (umc) 2-32 advanced v0.3 table 2-30 rtsx72su at v cci = 3.0v worst-case military conditions v cca = 2.25v, v cci = 3.0v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. dedicated (hardwired) array clock network t hckh pad to r-cell input low to high 3.2 3.8 ns t hckl pad to r-cell input high to low 3.5 4.1 ns t hpwh minimum pulse width high 2.7 3.2 ns t hpwl minimum pulse width low 2.7 3.2 ns t hcksw maximum skew 2.7 3.1 ns t hp minimum period 5.4 6.4 ns f hmax maximum frequency 185 156 mhz routed array clock networks t rckh pad to r-cell input low to high (light load)) 5.7 6.7 ns t rckl pad to r-cell input high to low (light load) 6.5 7.7 ns t rckh pad to r-cell input low to high (50% load) 5.7 6.7 ns t rckl pad to r-cell input high to low (50% load) 6.5 7.7 ns t rckh pad to r-cell input low to high (100% load) 5.7 6.7 ns t rckl pad to r-cell input high to low (100% load) 6.5 7.7 ns t rpwh minimum pulse width high 2.7 3.2 ns t rpwl minimum pulse width low 2.7 3.2 ns t rcksw maximum skew (light load) 5.1 6.0 ns t rcksw maximum skew (50% load) 4.9 5.8 ns t rcksw maximum skew (100% load) 4.9 5.8 ns t rp minimum period 5.4 6.4 ns f rmax maximum frequency 185 156 mhz quadrant array clock networks t qckh pad to r-cell input low to high (light load) 3.6 4.2 ns t qckl pad to r-cell input high to low (light load) 3.6 4.2 ns t qckh pad to r-cell input low to high (50% load) 3.7 4.3 ns t qckl pad to r-cell input high to low (50% load) 3.9 4.5 ns t qckh pad to r-cell input low to high (100% load) 4.0 4.7 ns t qckl pad to r-cell input high to low (100% load) 4.1 4.8 ns t qpwh minimum pulse width high 2.7 3.2 ns t qpwl minimum pulse width low 2.7 3.2 ns t qcksw maximum skew (light load) 0.6 0.7 ns t qcksw maximum skew (50% load) 1.0 1.1 ns t qcksw maximum skew (100% load) 1.0 1.1 ns t qp minimum period 5.4 6.4 ns f qmax maximum frequency 185 156 mhz
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-33 table 2-31 rtsx72su at v cci = 4.5v worst-case military conditions v cca = 2.25v, v cci = 4.5v, t j = 125c, radiation level = 0 krad (si) ??1? speed ?std.? speed units parameter description min. max. min. max. dedicated (hardwired) array clock network t hckh pad to r-cell input low to high 4.1 4.8 ns t hckl pad to r-cell input high to low 4.1 4.8 ns t hpwh minimum pulse width high 2.8 3.3 ns t hpwl minimum pulse width low 2.8 3.3 ns t hcksw maximum skew 3.2 3.7 ns t hp minimum period 5.6 6.6 ns f hmax maximum frequency 179 152 mhz routed array clock networks t rckh pad to r-cell input low to high (light load)) 6.8 8.0 ns t rckl pad to r-cell input high to low (light load) 8.2 9.7 ns t rckh pad to r-cell input low to high (50% load) 6.8 8.0 ns t rckl pad to r-cell input high to low (50% load) 8.2 9.7 ns t rckh pad to r-cell input low to high (100% load) 6.8 8.0 ns t rckl pad to r-cell input high to low (100% load) 8.2 9.7 ns t rpwh minimum pulse width high 2.8 3.3 ns t rpwl minimum pulse width low 2.8 3.3 ns t rcksw maximum skew (light load) 7.0 8.2 ns t rcksw maximum skew (50% load) 6.8 8.0 ns t rcksw maximum skew (100% load) 6.8 8.0 ns t qp minimum period 5.6 6.6 ns f qmax maximum frequency 179 152 mhz quadrant array clock networks t qckh pad to r-cell input low to high (light load)) 3.9 4.6 ns t qckl pad to r-cell input high to low (light load) 4.2 4.9 ns t qckh pad to r-cell input low to high (50% load) 4.2 4.9 ns t qckl pad to r-cell input high to low (50% load) 4.5 5.3 ns t qckh pad to r-cell input low to high (100% load) 4.5 5.3 ns t qckl pad to r-cell input high to low (100% load) 5.0 5.9 ns t qpwh minimum pulse width high 2.8 3.3 ns t qpwl minimum pulse width low 2.8 3.3 ns t qcksw maximum skew (light load) 0.7 0.8 ns t qcksw maximum skew (50% load) 1.3 1.5 ns t qcksw maximum skew (100% load) 1.4 1.6 ns t qp minimum period 5.6 6.6 ns f qmax maximum frequency 179 152 mhz
rtsx-su radtolerant fpgas (umc) 2-34 advanced v0.3 global resource access macros the user can configure which global resource is used in the design as well as how each global resource is driven through the use of the following macros: hclkbuf ? used to drive the hardwired clock (hclk) in both devices from an external pin clkbuf and clkbufi ? noninverting and inverting inputs used to drive eith er routed clock (clka or clkb) in both devices from external pins clkint and clkinti ? noninverting and inverting inputs used to drive eith er routed clock (clka or clkb) in both devices from internal logic qclkbuf and qclkbufi ? noninverting and inverting inputs used to drive quadrant routed clocks (qclka/b/c/d) in the rtsx72su from external pins qclkint and qclkinti ? noninverting and inverting inputs used to drive quadrant routed clocks (qclka/b/c/d) in the rtsx72su from internal logic qclkbibuf and qclukbibufi ? noninverting and inverting inputs used to drive quadrant routed clocks (qclka/b/c/d) in the rtsx72su alternatively from either external pins or internal logic figure 2-19 , figure 2-20 , and figure 2-21 illustrate the various global-resource access macros. figure 2-19 hardwired clock buffer constant load clock network hclkbuf figure 2-20 routed clock buffers in rtsx32su figure 2-21 routed and quadrant clock buffers in rtsx72su clock network from internal logic clkbuf clkbufi clkint clkinti clock network from internal logic from internal logic oe qclkbuf qclkbufi qclkint qclkinti qclkbibuf qclkbibufi clkbuf clkbufi clkint clkinti clkbibuf clkbibufi
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-35 other architectural features jtag interface all rtsx-su devices are ieee 1149.1 compliant and offer superior diagnostic and test ing capabilities by providing boundary scan testing (bst ) and probing capabilities. the bst function is controlled through special jtag pins (tms, tdi, tck, tdo, and trst ). the functionality of the jtag pins is defined by two available modes: dedicated and flexible ( table 2-32 ). note that trst and tms cannot be employed as user i/os in either mode. dedicated mode in dedicated mode, all jtag pins are reserved for bst; users cannot employ them as regular i/os. an internal pull-up resistor (on the order of 17 k ? to 22 k ? 2 ) is automatically enabled on both tms and tdi pins, and the tms pin will function as defined in the ieee 1149.1 (jtag) specification. to enter dedicated mode, users need to reserve the jtag pins in actel?s designer software during device selection. to reserve the jtag pins, users can check the "reserve jtag" box in the "device selection wizard" in actel?s designer software ( figure 2-22 ). flexible mode in flexible mode, tdi, tck, and tdo may be employed as either user i/os or as jt ag input pins. the internal resistors on the tms and tdi pins are not present in flexible jtag mode. to enter the flexible mode, users need to uncheck the "reserve jtag" box in the "device selection wizard" in designer software. tdi, tck, and tdo pins may function as user i/os or bst pins in flexible mode. this functionality is controlled by the bst tap controller. the tap controller receives two control inputs: tms and tck. upon power-up, the tap contro ller enters the test-logic- reset state. in this state, tdi, tck, and tdo function as user i/os. the tdi, tck, a nd tdo are transformed from user i/os into bst pins wh en a rising edge on tck is detected while tms is at logic low. to return to the test- logic-reset state, in the abse nces of trst assertion, tms must be held high for at least five tck cycles. an external, 10 k ? pull-up resistor tied to v cci should be placed on the tms pin to pull it high by default. table 2-33 describes the different configurations of the bst pins and their functionality in different modes. trst pin the trst pin functions as a dedicated boundary scan reset pin. an internal pull-up resistor is permanently enabled on the trst pin. additionally, the trst pin must be grounded for flight app lications. this will prevent single-event upsets (seu) in the tap controller from inadvertently placing the device into jtag mode. probing capabilities rtsx-su devices also provide internal probing capability that is accessed with the jtag pins. table 2-32 boundary scan pin functionality program fuse blown (dedicated test mode) program fuse not blown (flexible mode) tck, tdi, tdo are dedicated bst pins tck, tdi, tdo are flexible and may be used as user i/os no need for pull-up resistor for tms use a pull-up resistor of 10 k ? on tms 2. on a given device, the value of the inte rnal pull-up resistor varies within 1 k ? between the tms and tdi pins. figure 2-22 device selection wizard table 2-33 jtag pin configurations and functions mode designer "reserve jtag" selection tap controller state dedicated (jtag) checked any flexible (user i/o) unchecked test-logic-reset flexible (jtag) unchecked other
rtsx-su radtolerant fpgas (umc) 2-36 advanced v0.3 silicon explorer ii probe interface actel?s silicon explorer ii is an integrated hardware and software solution that, in conjunction with actel?s designer software, allows users to examine any of the internal nets of the device while it is operating in a prototype or a production system. the user can probe two nodes at a time without changing the placement or routing of the design and without using any additional device resources. highlighted nets in designer?s chipeditor can be accessed using silicon explorer ii in order to observe their real time values. silicon explorer ii's noninvas ive method does not alter timing or loading effects, thus shortening the debug cycle. in addition, silicon explorer ii does not require relayout or additional muxes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. by eliminating multiple place-a nd-route cycles, the integrity of the design is maintained throughout the debug process. both members of the rtsx-su family have two external pads: pra and prb. these can be used to bring out two probe signals from the device. to disallow probing, the sfus security fuse in the silicon signature has to be programmed. table 2-34 shows the possible device configuration options and their effects on probing. during probing, the silicon explorer ii diagnostic hardware is used to contro l the tdi, tck, tms, and tdo pins to select the desired nets for debugging. the user simply assigns the selected internal nets in the silicon explorer ii software to the pra/prb output pins for observation. probing functionality is activated when the bst pins are in jtag mode and the trst pin is driven high. if the trst pin is held low, the tap controller will remain in the test-logic-reset state, so no probing can be performed. silicon explorer ii automatically places the device into jtag mode, but the user must drive the trst pin high or allow the internal pull-up resistor to pull trst high. silicon explorer ii connects to the host pc using a standard serial port connector. connections to the circuit board are achieved using a nine-pin d-sub connector ( figure 1-5 on page 1-6 ). once the design has been placed-and-routed and the rtsx-su device has been programmed, silicon explorer ii can be connected and the silicon explorer software can be launched. silicon explorer ii comes with an additional optional pc- hosted tool that emulates an 18-channel logic analyzer. two channels are used to monitor two internal nodes, and 16 channels are available to probe external signals. the software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. table 2-34 device configuration options for probe capability jtag mode trst security fuse programmed pra and prb 1 tdi, tck, and tdo 1 dedicated low no user i/o 2 probing unavailable flexible low no user i/o 2 user i/o 2 dedicated high no probe circuit outputs probe circuit i/o flexible high no probe circuit outputs probe circuit i/o ? ? yes probe circuit secured probe circuit secured notes: 1. avoid using the tdi, tck, tdo, pra, and prb pins as input or bidirectional ports during probing. since these pins are active during probing, input signals will not pass through these pins and may cause contention. 2. if no user signal is assigned to these pins, they will behave as unused i/os in this mode. unused pins are automatically tris tated by the designer software.
rtsx-su radtolerant fpgas (umc) advanced v0.3 2-37 security fuses actel antifuse fpgas, with fuselock technology, offer the highest level of design security available in a programmable logic device. since antifuse fpgas are live at power-up, ther e is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the de vice, thus making device cloning impossible. in addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attemp ting to exploit either the programming or probing inte rfaces. both invasive and noninvasive attacks against an rtsx-su device that access or bypass these securi ty fuses will destroy access to the rest of the device. refer to the understanding actel antifuse device security white paper for more information. look for this symbol to ensure your valuable ip is secure ( figure 2-23 ). to ensure maximum security in rtsx-su devices, it is recommended that the user program the device security fuse (sfus). when programme d, the silicon explorer ii testing probes are disabled to prevent internal probing, and the programming interface is also disabled. all jtag public instructions are still accessible by the user. for more information, refer to actel?s implementation of security in actel antifuse fpgas application note. programming device programming is supp orted through the silicon sculptor ii, a single-site, robust and compact device- programmer for the pc. two silicon sculptor iis can be daisy-chained and controlled from a single pc host. with standalone software for th e pc, silicon sculptor ii is designed to allow concurrent programming of multiple units from the same pc when daisy-chained. silicon sculptor ii programs devices independently to achieve the fastest programming times possible. each fuse is verified by silicon sculptor ii to ensure correct programming. furthermore, at the end of programming, there are integrity tests th at are run to ensure that programming was completed properly. not only does it test programmed and nonprogrammed fuses, silicon sculptor ii also provides a self -test to extensively test its own hardware. programming an rtsx-su device using silicon sculptor ii is similar to programming any other antifuse device. the procedure is as follows: 1. load the .afm file 2. select the device to be programmed 3. begin programming when the design is ready to go to production, actel offers volume programming services either through distribution partners or via our in-house programming center. for more details on programming the rtsx-su devices, please refer to the silicon sculptor ii user?s guide . figure 2-23 fuselock logo ? e u

rtsx-su radtolerant fpgas (umc) advanced v0.3 3-1 package pin assignments 208-pin cqfp figure 3-1 208-pin cqfp (top view) ceramic tie bar 208-pin cqfp 1 2 3 4 49 50 51 52 53 54 55 56 101 102 103 104 156 155 154 153 108 107 106 105 208 207 206 205 160 159 158 157 pin 1
rtsx-su radtolerant fpgas (umc) 3-2 advanced v0.3 208-pin cqfp pin number rtsx32su function rtsx72su function 1gndgnd 2 tdi, i/o tdi, i/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o i/o 11 tms tms 12 v cci v cci 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 i/o gnd 19 i/o v cca 20 i/o i/o 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 nc i/o 26 gnd gnd 27 v cca v cca 28 gnd gnd 29 i/o i/o 30 trst trst 31 i/o i/o 32 i/o i/o 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208. 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 v cci v cci 41 v cca v cca 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 i/o i/o 51 i/o i/o 52 gnd gnd 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 i/o i/o 60 v cci v cci 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 nc i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 71 i/o i/o 72 i/o i/o 208-pin cqfp pin number rtsx32su function rtsx72su function note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-3 73 i/o i/o 74 i/o qclka, i/o 75 i/o i/o 76 prb, i/o prb, i/o 77 gnd gnd 78 v cca v cca 79 gnd gnd 80 nc nc 81 i/o i/o 82 hclk hclk 83 i/o v cci 84 i/o qclkb, i/o 85 i/o i/o 86 i/o i/o 87 i/o i/o 88 i/o i/o 89 i/o i/o 90 i/o i/o 91 i/o i/o 92 i/o i/o 93 i/o i/o 94 i/o i/o 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 v cci v cci 99 i/o i/o 100 i/o i/o 101 i/o i/o 102 i/o i/o 103 tdo, i/o tdo, i/o 104 i/o i/o 105 gnd gnd 106 i/o i/o 107 i/o i/o 108 i/o i/o 208-pin cqfp pin number rtsx32su function rtsx72su function note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208. 109 i/o i/o 110 i/o i/o 111 i/o i/o 112 i/o i/o 113 i/o i/o 114 v cca v cca 115 v cci v cci 116 i/o gnd 117 i/o v cca 118 i/o i/o 119 i/o i/o 120 i/o i/o 121 i/o i/o 122 i/o i/o 123 i/o i/o 124 i/o i/o 125 i/o i/o 126 i/o i/o 127 i/o i/o 128 i/o i/o 129 gnd gnd 130 v cca v cca 131 gnd gnd 132 nc i/o 133 i/o i/o 134 i/o i/o 135 i/o i/o 136 i/o i/o 137 i/o i/o 138 i/o i/o 139 i/o i/o 140 i/o i/o 141 i/o i/o 142 i/o i/o 143 i/o i/o 144 i/o i/o 208-pin cqfp pin number rtsx32su function rtsx72su function note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208.
rtsx-su radtolerant fpgas (umc) 3-4 advanced v0.3 145 v cca v cca 146 gnd gnd 147 i/o i/o 148 v cci v cci 149 i/o i/o 150 i/o i/o 151 i/o i/o 152 i/o i/o 153 i/o i/o 154 i/o i/o 155 i/o i/o 156 i/o i/o 157 gnd gnd 158 i/o i/o 159 i/o i/o 160 i/o i/o 161 i/o i/o 162 i/o i/o 163 i/o i/o 164 v cci v cci 165 i/o i/o 166 i/o i/o 167 i/o i/o 168 i/o i/o 169 i/o i/o 170 i/o i/o 171 i/o i/o 172 i/o i/o 173 i/o i/o 174 i/o i/o 175 i/o i/o 176 i/o i/o 177 i/o i/o 178 i/o qclkd, i/o 179 i/o i/o 180 clka clka, i/o 208-pin cqfp pin number rtsx32su function rtsx72su function note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208. 181 clkb clkb, i/o 182 nc nc 183 gnd gnd 184 v cca v cca 185 gnd gnd 186 pra, i/o pra, i/o 187 i/o v cci 188 i/o i/o 189 i/o i/o 190 i/o qclkc, i/o 191 i/o i/o 192 i/o i/o 193 i/o i/o 194 i/o i/o 195 i/o i/o 196 i/o i/o 197 i/o i/o 198 i/o i/o 199 i/o i/o 200 i/o i/o 201 v cci v cci 202 i/o i/o 203 i/o i/o 204 i/o i/o 205 i/o i/o 206 i/o i/o 207 i/o i/o 208 tck, i/o tck, i/o 208-pin cqfp pin number rtsx32su function rtsx72su function note: pin 65 is a no connect (nc) on commercial a54sx32s- pq208.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-5 256-pin cqfp figure 3-2 256-pin cqfp (top view) ceramic tie bar 256-pin cqfp 1 2 3 4 61 62 63 64 65 66 67 68 125 126 127 128 192 191 190 189 132 131 130 129 256 255 254 253 196 195 194 193 pin 1
rtsx-su radtolerant fpgas (umc) 3-6 advanced v0.3 256-pin cqfp pin number rtsx32su function rtsx72su function 1gndgnd 2 tdi, i/o tdi, i/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o i/o 11 tms tms 12 i/o i/o 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o v cci 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 v cci v cci 29 gnd gnd 30 v cca v cca 31 gnd gnd 32 i/o i/o 33 i/o i/o 34 trst trst 35 i/o i/o 36 i/o v cca 37 i/o gnd 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 v cca v cca 47 i/o v cci 48 i/o i/o 49 i/o i/o 50 i/o i/o 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o gnd 57 i/o i/o 58 i/o i/o 59 gnd gnd 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 71 i/o i/o 72 i/o i/o 73 i/o v cci 74 i/o i/o 256-pin cqfp pin number rtsx32su function rtsx72su function
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-7 75 i/o i/o 76 i/o i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 85 i/o i/o 86 i/o i/o 87 i/o i/o 88 i/o i/o 89 i/o qclka, i/o 90 prb, i/o prb, i/o 91 gnd gnd 92 v cci v cci 93 gnd gnd 94 v cca v cca 95 i/o i/o 96 hclk hclk 97 i/o i/o 98 i/o qclkb, i/o 99 i/o i/o 100 i/o i/o 101 i/o i/o 102 i/o i/o 103 i/o i/o 104 i/o i/o 105 i/o i/o 106 i/o i/o 107 i/o i/o 108 i/o i/o 109 i/o i/o 110 gnd gnd 111 i/o i/o 256-pin cqfp pin number rtsx32su function rtsx72su function 112 i/o i/o 113 i/o i/o 114 i/o i/o 115 i/o i/o 116 i/o i/o 117 i/o i/o 118 i/o i/o 119 i/o i/o 120 i/o v cci 121 i/o i/o 122 i/o i/o 123 i/o i/o 124 i/o i/o 125 i/o i/o 126 tdo, i/o tdo, i/o 127 i/o i/o 128 gnd gnd 129 i/o i/o 130 i/o i/o 131 i/o i/o 132 i/o i/o 133 i/o i/o 134 i/o i/o 135 i/o i/o 136 i/o i/o 137 i/o i/o 138 i/o i/o 139 i/o i/o 140 i/o i/o 141 v cca v cca 142 i/o v cci 143 i/o gnd 144 i/o v cca 145 i/o i/o 146 i/o i/o 147 i/o i/o 148 i/o i/o 256-pin cqfp pin number rtsx32su function rtsx72su function
rtsx-su radtolerant fpgas (umc) 3-8 advanced v0.3 149 i/o i/o 150 i/o i/o 151 i/o i/o 152 i/o i/o 153 i/o i/o 154 i/o i/o 155 i/o i/o 156 i/o i/o 157 i/o i/o 158 gnd gnd 159 nc nc 160 gnd gnd 161 v cci v cci 162 i/o v cca 163 i/o i/o 164 i/o i/o 165 i/o i/o 166 i/o i/o 167 i/o i/o 168 i/o i/o 169 i/o i/o 170 i/o i/o 171 i/o i/o 172 i/o i/o 173 i/o i/o 174 v cca v cca 175 gnd gnd 176 gnd gnd 177 i/o i/o 178 i/o i/o 179 i/o i/o 180 i/o i/o 181 i/o i/o 182 i/o i/o 183 i/o v cci 184 i/o i/o 185 i/o i/o 256-pin cqfp pin number rtsx32su function rtsx72su function 186 i/o i/o 187 i/o i/o 188 i/o i/o 189 gnd gnd 190 i/o i/o 191 i/o i/o 192 i/o i/o 193 i/o i/o 194 i/o i/o 195 i/o i/o 196 i/o i/o 197 i/o i/o 198 i/o i/o 199 i/o i/o 200 i/o i/o 201 i/o i/o 202 i/o v cci 203 i/o i/o 204 i/o i/o 205 i/o i/o 206 i/o i/o 207 i/o i/o 208 i/o i/o 209 i/o i/o 210 i/o i/o 211 i/o i/o 212 i/o i/o 213 i/o i/o 214 i/o i/o 215 i/o i/o 216 i/o i/o 217 i/o i/o 218 i/o qclkd, i/o 219 clka clka, i/o 220 clkb clkb, i/o 221 v cci v cci 222 gnd gnd 256-pin cqfp pin number rtsx32su function rtsx72su function
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-9 223 nc nc 224 gnd gnd 225 pra, i/o pra, i/o 226 i/o i/o 227 i/o i/o 228 i/o v cca 229 i/o i/o 230 i/o i/o 231 i/o qclkc, i/o 232 i/o i/o 233 i/o i/o 234 i/o i/o 235 i/o i/o 236 i/o i/o 237 i/o i/o 238 i/o i/o 239 i/o i/o 240 gnd gnd 241 i/o i/o 242 i/o i/o 243 i/o i/o 244 i/o i/o 245 i/o i/o 246 i/o i/o 247 i/o i/o 248 i/o i/o 249 i/o v cci 250 i/o i/o 251 i/o i/o 252 i/o i/o 253 i/o i/o 254 i/o i/o 255 i/o i/o 256 tck, i/o tck, i/o 256-pin cqfp pin number rtsx32su function rtsx72su function
rtsx-su radtolerant fpgas (umc) 3-10 advanced v0.3 256-pin cclg figure 3-3 256-pin cclg 1 64 65 128 129 192 193 256 a1 index corner extenral wire-bond number bottom view top view a b c d e f g h j k l m n p r t 12 3456 78910111213141516
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-11 256-pin cclg* pin number external wire- bond number rtsx32su function a1 1 gnd a2 256 tck, i/o a3 255 i/o a4 251 i/o a5 243 i/o a6 238 i/o a7 232 i/o a8 228 i/o a9 227 clkb a10 221 i/o a11 216 i/o a12 209 i/o a13 203 i/o a14 200 i/o a15 2 gnd a16 13 gnd b1 242 i/o b2 22 gnd b3 254 i/o b4 253 i/o b5 248 i/o b6 241 i/o b7 234 i/o b8 33 v cca b9 222 i/o b10 220 i/o b11 212 i/o b12 207 i/o b13 202 i/o b14 198 i/o b15 32 gnd b16 196 i/o c16i/o c2 4 tdi,i/o note: *this table was sorted by the pin number. c3 65 gnd c4 252 i/o c5 249 i/o c6 245 i/o c7 239 i/o c8 230 i/o c9 226 clka c10 218 i/o c11 210 i/o c12 201 i/o c13 197 i/o c14 211 i/o c15 178 i/o c16 195 i/o d1 12 i/o d2 8 i/o d3 10 i/o d4 7 i/o d5 250 i/o d6 244 i/o d7 237 i/o d8 229 pra, i/o d9 217 i/o d10 208 i/o d11 206 i/o d12 199 i/o d13 205 i/o d14 173 i/o d15 190 i/o d16 188 i/o e1 16 i/o e2 15 i/o e3 9 i/o e4 11 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number.
rtsx-su radtolerant fpgas (umc) 3-12 advanced v0.3 e5 5 i/o e6 240 i/o e7 233 i/o e8 231 i/o e9 223 i/o e10 219 i/o e11 213 i/o e12 167 i/o e13 183 i/o e14 189 i/o e15 187 i/o e16 186 i/o f1 17 i/o f2 18 i/o f3 20 i/o f4 14 tms f5 19 i/o f6 28 i/o f7 3 v cci f8 23 v cci f9 44 v cci f10 55 v cci f11 157 i/o f12 97 v cca f13 177 i/o f14 185 i/o f15 184 i/o f16 181 i/o g1 24 i/o g2 25 i/o g3 27 i/o g4 26 i/o g5 21 i/o g6 66 v cci 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number. g7 43 gnd g8 54 gnd g9 67 gnd g10 77 gnd g11 87 v cci g12 169 i/o g13 180 gnd g14 176 i/o g15 179 v cca g16 175 i/o h1 29 i/o h2 31 i/o h3 160 v cca h4 35 trst h5 37 i/o h6 108 v cci h7 86 gnd h8 96 gnd h9 107 gnd h10 118 gnd h11 128 v cci h12 165 i/o h13 170 i/o h14 168 i/o h15 166 i/o h16 174 i/o j1 30 i/o j2 38 i/o j3 40 i/o j4 41 i/o j5 39 i/o j6 139 v cci j7 127 gnd j8 140 gnd 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-13 j9 151 gnd j10 161 gnd j11 150 v cci j12 159 i/o j13 163 i/o j14 164 i/o j15 162 i/o j16 158 i/o k1 34 i/o k2 45 i/o k3 47 i/o k4 50 v cca k5 48 i/o k6 171 v cci k7 172 gnd k8 182 gnd k9 192 gnd k10 204 gnd k11 191 v cci k12 153 i/o k13 155 i/o k14 156 i/o k15 152 i/o k16 154 i/o l1 36 i/o l2 46 i/o l3 51 i/o l4 58 i/o l5 52 i/o l6 91 i/o l7 194 v cci l8 214 v cci l9 235 v cci l10 246 v cci 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number. l11 103 i/o l12 149 i/o l13 146 i/o l14 148 i/o l15 145 i/o l16 147 i/o m1 42 i/o m2 53 i/o m3 61 i/o m4 60 i/o m5 72 i/o m6 81 i/o m7 89 i/o m8 95 prb, i/o m9 101 i/o m10 105 i/o m11 114 i/o m12 111 i/o m13 141 i/o m14 142 i/o m15 137 i/o m16 144 i/o n1 49 i/o n2 57 i/o n3 63 i/o n4 79 i/o n5 70 i/o n6 76 i/o n7 83 i/o n8 99 i/o n9 109 i/o n10 117 i/o n11 112 i/o n12 124 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number.
rtsx-su radtolerant fpgas (umc) 3-14 advanced v0.3 n13 121 i/o n14 133 i/o n15 135 i/o n16 136 i/o p1 59 i/o p2 138 gnd p3 56 i/o p4 74 i/o p5 64 i/o p6 82 i/o p7 90 i/o p8 94 i/o p9 104 i/o p10 113 i/o p11 119 i/o p12 123 i/o p13 143 v cca p14 131 i/o p15 132 i/o p16 134 i/o r1 62 i/o r2 215 gnd r3 68 i/o r4 73 i/o r5 78 i/o r6 85 i/o r7 92 i/o r8 98 i/o r9 100 hclk r10 106 i/o r11 115 i/o r12 120 i/o r13 126 i/o r14 130 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number. r15 225 gnd r16 193 gnd t1 236 gnd t2 69 i/o t3 71 i/o t4 75 i/o t5 80 i/o t6 84 i/o t7 88 i/o t8 93 i/o t9 224 v cca t10 102 i/o t11 110 i/o t12 116 i/o t13 122 i/o t14 125 i/o t15 129 tdo,i/o t16 247 gnd 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the pin number.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-15 256-pin cclg* pin number external wire- bond number rtsx32su function a1 1 gnd a15 2 gnd f7 3 v cci c2 4 tdi,i/o e5 5 i/o c16i/o d47i/o d28i/o e3 9 i/o d3 10 i/o e4 11 i/o d1 12 i/o a16 13 gnd f4 14 tms e2 15 i/o e1 16 i/o f1 17 i/o f2 18 i/o f5 19 i/o f3 20 i/o g5 21 i/o b2 22 gnd f8 23 v cci g1 24 i/o g2 25 i/o g4 26 i/o g3 27 i/o f6 28 i/o h1 29 i/o j1 30 i/o h2 31 i/o b15 32 gnd b8 33 v cca k1 34 i/o note: *this table was sorted by the wire-bond number. h4 35 trst l1 36 i/o h5 37 i/o j2 38 i/o j5 39 i/o j3 40 i/o j4 41 i/o m1 42 i/o g7 43 gnd f9 44 v cci k2 45 i/o l2 46 i/o k3 47 i/o k5 48 i/o n1 49 i/o k4 50 v cca l3 51 i/o l5 52 i/o m2 53 i/o g8 54 gnd f10 55 v cci p3 56 i/o n2 57 i/o l4 58 i/o p1 59 i/o m4 60 i/o m3 61 i/o r1 62 i/o n3 63 i/o p5 64 i/o c3 65 gnd g6 66 v cci g9 67 gnd r3 68 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number.
rtsx-su radtolerant fpgas (umc) 3-16 advanced v0.3 t2 69 i/o n5 70 i/o t3 71 i/o m5 72 i/o r4 73 i/o p4 74 i/o t4 75 i/o n6 76 i/o g10 77 gnd r5 78 i/o n4 79 i/o t5 80 i/o m6 81 i/o p6 82 i/o n7 83 i/o t6 84 i/o r6 85 i/o h7 86 gnd g11 87 v cci t7 88 i/o m7 89 i/o p7 90 i/o l6 91 i/o r7 92 i/o t8 93 i/o p8 94 i/o m8 95 prb, i/o h8 96 gnd f12 97 v cca r8 98 i/o n8 99 i/o r9 100 hclk m9 101 i/o t10 102 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number. l11 103 i/o p9 104 i/o m10 105 i/o r10 106 i/o h9 107 gnd h6 108 v cci n9 109 i/o t11 110 i/o m12 111 i/o n11 112 i/o p10 113 i/o m11 114 i/o r11 115 i/o t12 116 i/o n10 117 i/o h10 118 gnd p11 119 i/o r12 120 i/o n13 121 i/o t13 122 i/o p12 123 i/o n12 124 i/o t14 125 i/o r13 126 i/o j7 127 gnd h11 128 v cci t15 129 tdo,i/o r14 130 i/o p14 131 i/o p15 132 i/o n14 133 i/o p16 134 i/o n15 135 i/o n16 136 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-17 m15 137 i/o p2 138 gnd j6 139 v cci j8 140 gnd m13 141 i/o m14 142 i/o p13 143 v cca m16 144 i/o l15 145 i/o l13 146 i/o l16 147 i/o l14 148 i/o l12 149 i/o j11 150 v cci j9 151 gnd k15 152 i/o k12 153 i/o k16 154 i/o k13 155 i/o k14 156 i/o f11 157 i/o j16 158 i/o j12 159 i/o h3 160 v cca j10 161 gnd j15 162 i/o j13 163 i/o j14 164 i/o h12 165 i/o h15 166 i/o e12 167 i/o h14 168 i/o g12 169 i/o h13 170 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number. k6 171 v cci k7 172 gnd d14 173 i/o h16 174 i/o g16 175 i/o g14 176 i/o f13 177 i/o c15 178 i/o g15 179 v cca g13 180 gnd f16 181 i/o k8 182 gnd e13 183 i/o f15 184 i/o f14 185 i/o e16 186 i/o e15 187 i/o d16 188 i/o e14 189 i/o d15 190 i/o k11 191 v cci k9 192 gnd r16 193 gnd l7 194 v cci c16 195 i/o b16 196 i/o c13 197 i/o b14 198 i/o d12 199 i/o a14 200 i/o c12 201 i/o b13 202 i/o a13 203 i/o k10 204 gnd 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number.
rtsx-su radtolerant fpgas (umc) 3-18 advanced v0.3 d13 205 i/o d11 206 i/o b12 207 i/o d10 208 i/o a12 209 i/o c11 210 i/o c14 211 i/o b11 212 i/o e11 213 i/o l8 214 v cci r2 215 gnd a11 216 i/o d9 217 i/o c10 218 i/o e10 219 i/o b10 220 i/o a10 221 i/o b9 222 i/o e9 223 i/o t9 224 v cca r15 225 gnd c9 226 clka a9 227 clkb a8 228 i/o d8 229 pra, i/o c8 230 i/o e8 231 i/o a7 232 i/o e7 233 i/o b7 234 i/o l9 235 v cci t1 236 gnd d7 237 i/o a6 238 i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number. c7 239 i/o e6 240 i/o b6 241 i/o b1 242 i/o a5 243 i/o d6 244 i/o c6 245 i/o l10 246 v cci t16 247 gnd b5 248 i/o c5 249 i/o d5 250 i/o a4 251 i/o c4 252 i/o b4 253 i/o b3 254 i/o a3 255 i/o a2 256 tck, i/o 256-pin cclg* pin number external wire- bond number rtsx32su function note: *this table was sorted by the wire-bond number.
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-19 624-pin ccga figure 3-4 624-pin ccga (b ottom view) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y a a ac ab ad ae
rtsx-su radtolerant fpgas (umc) 3-20 advanced v0.3 624-pin ccga pin number rtsx72su function a2 nc a3 nc a4 nc a5 i/o a6 i/o a7 i/o a8 i/o a9 i/o a10 i/o a11 i/o a12 i/o a13 gnd a14 i/o a15 i/o a16 i/o a17 i/o a18 i/o a19 i/o a20 i/o a21 i/o a22 gnd a23 nc a24 nc a25 nc b1 nc b2 gnd b3 gnd b4 v cci b5 gnd b6 i/o b7 i/o b8 v cci b9 gnd b10 i/o b11 i/o b12 i/o b13 i/o b14 clkb, i/o b15 i/o b16 i/o b17 i/o b18 i/o b19 i/o b20 i/o b21 i/o b22 gnd b23 v cci b24 gnd b25 nc c1 nc c2 v cci c3 gnd c4 i/o c5 i/o c6 i/o c7 i/o c8 i/o c9 i/o c10 i/o c11 qclkc, i/o c12 i/o c13 pra, i/o c14 clka, i/o c15 i/o c16 i/o c17 i/o c18 i/o c19 i/o c20 i/o c21 i/o 624-pin ccga pin number rtsx72su function c22 i/o c23 gnd c24 v cci c25 nc d1 gnd d2 gnd d3 tdi d4 gnd d5 i/o d6 i/o d7 i/o d8 i/o d9 i/o d10 i/o d11 i/o d12 i/o d13 i/o d14 qclkd, i/o d15 i/o d16 i/o d17 i/o d18 i/o d19 i/o d20 i/o d21 i/o d22 v cci d23 gnd d24 gnd d25 gnd e1 i/o e2 i/o e3 i/o e4 i/o e5 tck, i/o e6 i/o 624-pin ccga pin number rtsx72su function
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-21 e7 i/o e8 i/o e9 i/o e10 i/o e11 i/o e12 v cca e13 gnd e14 i/o e15 i/o e16 i/o e17 i/o e18 i/o e19 i/o e20 i/o e21 i/o e22 i/o e23 i/o e24 i/o e25 i/o f1 i/o f2 v cci f3 i/o f4 i/o f5 i/o f6 nc f7 nc f8 i/o f9 nc f10 nc f11 nc f12 nc f13 i/o f14 i/o f15 nc f16 gnd 624-pin ccga pin number rtsx72su function f17 i/o f18 i/o f19 i/o f20 i/o f21 i/o f22 i/o f23 i/o f24 i/o f25 i/o g1 i/o g2 i/o g3 tms g4 i/o g5 i/o g6 i/o g7 v cci g8 nc g9 nc g10 nc g11 nc g12 nc g13 nc g14 nc g15 nc g16 nc g17 nc g18 gnd g19 v cci g20 i/o g21 i/o g22 i/o g23 i/o g24 i/o g25 i/o h1 i/o 624-pin ccga pin number rtsx72su function h2 i/o h3 i/o h4 i/o h5 i/o h6 i/o h7 i/o h8 v cci h9 nc h10 nc h11 nc h12 nc h13 nc h14 nc h15 nc h16 nc h17 nc h18 v cci h19 i/o h20 i/o h21 i/o h22 i/o h23 i/o h24 gnd h25 i/o j1 i/o j2 i/o j3 i/o j4 i/o j5 i/o j6 i/o j7 nc j8 nc j9 v cci j10 nc j11 nc 624-pin ccga pin number rtsx72su function
rtsx-su radtolerant fpgas (umc) 3-22 advanced v0.3 j12 nc j13 nc j14 nc j15 nc j16 nc j17 v cci j18 nc j19 nc j20 i/o j21 v cca j22 i/o j23 i/o j24 i/o j25 i/o k1 i/o k2 gnd k3 i/o k4 i/o k5 i/o k6 gnd k7 nc k8 nc k9 nc k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd k16 gnd k17 nc k18 nc k19 nc k20 i/o k21 i/o 624-pin ccga pin number rtsx72su function k22 i/o k23 i/o k24 i/o k25 i/o l1 i/o l2 i/o l3 i/o l4 i/o l5 i/o l6 i/o l7 nc l8 nc l9 nc l10 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l17 nc l18 nc l19 nc l20 i/o l21 i/o l22 i/o l23 i/o l24 i/o l25 i/o m1 i/o m2 i/o m3 i/o m4 i/o m5 gnd m6 i/o 624-pin ccga pin number rtsx72su function m7 nc m8 nc m9 nc m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 nc m18 nc m19 nc m20 i/o m21 gnd m22 i/o m23 i/o m24 gnd m25 i/o n1 i/o n2 i/o n3 i/o n4 i/o n5 v cca n6 i/o n7 v cca n8 nc n9 nc n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd 624-pin ccga pin number rtsx72su function
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-23 n17 nc n18 nc n19 v cca n20 i/o n21 v cca n22 i/o n23 i/o n24 v cci n25 i/o p1 i/o p2 i/o p3 i/o p4 i/o p5 i/o p6 i/o p7 nc p8 nc p9 nc p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 nc p18 nc p19 nc p20 i/o p21 gnd p22 i/o p23 i/o p24 i/o p25 i/o r1 i/o 624-pin ccga pin number rtsx72su function r2 i/o r3 i/o r4 trst r5 i/o r6 gnd r7 nc r8 nc r9 nc r10 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 nc r18 nc r19 nc r20 i/o r21 i/o r22 i/o r23 i/o r24 i/o r25 i/o t1 i/o t2 i/o t3 i/o t4 i/o t5 i/o t6 i/o t7 i/o t8 nc t9 nc t10 gnd t11 gnd 624-pin ccga pin number rtsx72su function t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 nc t18 nc t19 nc t20 gnd t21 i/o t22 i/o t23 i/o t24 i/o t25 i/o u1 i/o u2 i/o u3 i/o u4 i/o u5 i/o u6 i/o u7 i/o u8 nc u9 v cci u10 nc u11 nc u12 nc u13 nc u14 nc u15 nc u16 nc u17 v cci u18 nc u19 nc u20 i/o u21 i/o 624-pin ccga pin number rtsx72su function
rtsx-su radtolerant fpgas (umc) 3-24 advanced v0.3 u22 i/o u23 i/o u24 i/o u25 i/o v1 i/o v2 i/o v3 i/o v4 v cca v5 i/o v6 i/o v7 gnd v8 v cci v9 nc v10 nc v11 nc v12 nc v13 nc v14 nc v15 nc v16 nc v17 nc v18 v cci v19 i/o v20 i/o v21 i/o v22 v cca v23 i/o v24 i/o v25 i/o w1 i/o w2 v cci w3 i/o w4 i/o w5 i/o w6 i/o 624-pin ccga pin number rtsx72su function w7 vcci w8 nc w9 nc w10 nc w11 nc w12 nc w13 nc w14 nc w15 nc w16 nc w17 nc w18 i/o w19 v cci w20 i/o w21 i/o w22 i/o w23 i/o w24 i/o w25 i/o y1 i/o y2 i/o y3 i/o y4 i/o y5 i/o y6 i/o y7 i/o y8 i/o y9 i/o y10 i/o y11 nc y12 gnd y13 i/o y14 nc y15 gnd y16 i/o 624-pin ccga pin number rtsx72su function y17 i/o y18 i/o y19 i/o y20 i/o y21 i/o y22 i/o y23 i/o y24 gnd y25 i/o aa1 gnd aa2 gnd aa3 i/o aa4 i/o aa5 gnd aa6 i/o aa7 i/o aa8 i/o aa9 i/o aa10 i/o aa11 i/o aa12 i/o aa13 v cca aa14 gnd aa15 i/o aa16 i/o aa17 i/o aa18 i/o aa19 i/o aa20 i/o aa21 gnd aa22 i/o aa23 i/o aa24 i/o aa25 gnd ab1 nc 624-pin ccga pin number rtsx72su function
rtsx-su radtolerant fpgas (umc) advanced v0.3 3-25 ab2 v cci ab3 i/o ab4 gnd ab5 i/o ab6 i/o ab7 i/o ab8 i/o ab9 i/o ab10 i/o ab11 i/o ab12 qclka, i/o ab13 i/o ab14 i/o ab15 i/o ab16 i/o ab17 i/o ab18 i/o ab19 i/o ab20 i/o ab21 tdo, i/o ab22 v cci ab23 i/o ab24 v cci ab25 nc ac1 nc ac2 i/o ac3 gnd ac4 i/o ac5 i/o ac6 i/o ac7 i/o ac8 i/o ac9 i/o ac10 i/o ac11 i/o 624-pin ccga pin number rtsx72su function ac12 prb, i/o ac13 i/o ac14 hclk ac15 i/o ac16 i/o ac17 i/o ac18 i/o ac19 i/o ac20 i/o ac21 i/o ac22 i/o ac23 gnd ac24 i/o ac25 nc ad1 nc ad2 gnd ad3 v cci ad4 gnd ad5 i/o ad6 i/o ad7 i/o ad8 i/o ad9 i/o ad10 v cci ad11 i/o ad12 i/o ad13 i/o ad14 i/o ad15 i/o ad16 gnd ad17 i/o ad18 i/o ad19 i/o ad20 i/o ad21 i/o 624-pin ccga pin number rtsx72su function ad22 gnd ad23 v cci ad24 gnd ad25 nc ae1 nc ae2 nc ae3 nc ae4 gnd ae5 i/o ae6 i/o ae7 i/o ae8 i/o ae9 i/o ae10 i/o ae11 i/o ae12 i/o ae13 i/o ae14 qclkb, i/o ae15 i/o ae16 i/o ae17 i/o ae18 i/o ae19 i/o ae20 i/o ae21 i/o ae22 gnd ae23 nc ae24 nc ae25 nc 624-pin ccga pin number rtsx72su function

rtsx-su radtolerant fpgas (umc) advanced v0.3 4-1 datasheet information list of changes the following table lists critical changes that were made to the current version of the document. datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. previous version changes in current version (advanced v0.3) page advanced v0.2 in ta b l e 2 - 1 3 , the i oh = ?20 a and i ol = 20 a. 2-14 advanced v0.1 ta b l e 2 - 8 was updated. 2-5 ta b l e 2 - 1 1 and ta b l e 2 - 1 2 were updated. 2-12 , 2-13 ta b l e 2 - 1 4 and ta b l e 2 - 1 5 were updated. 2-14 , 2-15 ta b l e 2 - 1 8 and ta b l e 2 - 1 9 were updated. 2-18 , 2-18 ta b l e 2 - 2 2 and ta b l e 2 - 2 3 were updated. 2-21 , 2-21 ta b l e 2 - 2 5 was updated. 2-26 ta b l e 2 - 2 6 and ta b l e 2 - 2 7 were updated. 2-28 , 2-28 ta b l e 2 - 2 8 and ta b l e 2 - 2 9 were updated. 2-30 , 2-31 ta b l e 2 - 3 0 and ta b l e 2 - 3 1 were updated. 2-32 , 2-33
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